verilog

gowin/fpga_project/src/bit3adder.v

@@ -0,0 +1,13 @@
+module bit3adder(
+    input [2:0] A,
+    input [2:0] B,
+    output [3:0] C
+);
+
+wire c1,c2,c3,c4;
+
+halfadder ha0(A[0], B[0], C[0], c1);
+fulladder fa0(A[1], B[1], c1, C[1], c2);
+fulladder fa1(A[2], B[2], c2, C[2], C[3]);
+
+endmodule

gowin/fpga_project/src/fpga_project.cst

@@ -0,0 +1,15 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved. 
+//File Title: Physical Constraints file
+//Tool Version: V1.9.9.03 Education (64-bit)
+//Part Number: GW2A-LV18PG256C8/I7
+//Device: GW2A-18
+//Device Version: C
+//Created Time: Fri 07 05 01:47:34 2024
+
+IO_LOC "L14[2]" L16;
+IO_PORT "L14[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "L14[1]" L14;
+IO_PORT "L14[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "L14[0]" N14;
+IO_PORT "L14[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;

gowin/fpga_project/src/fulladder.v

@@ -0,0 +1,13 @@
+module fulladder(
+    input A, B, C0,
+    output S, C
+);
+
+wire S1,C1,C2;
+
+halfadder ha1(A, B, S1, C1);
+halfadder ha2(S1, C0, S, C2);
+
+or (C, C2, C1);
+
+endmodule

gowin/fpga_project/src/halfadder.v

@@ -0,0 +1,9 @@
+module halfadder(
+    input A,B,
+    output S,C
+);
+
+xor (S, A, B);
+and (C, A, B);
+
+endmodule

gowin/fpga_project/src/ledTest.v

@@ -0,0 +1,31 @@
+module ledTest (
+    input[1:0] v1, v2,
+    output reg[2:0] L14
+);
+
+wire[3:0] sum;
+
+bit3adder adder(
+    .A({1'b0, v1}),
+    .B({1'b0, v2}),
+    .C(sum)
+);
+
+
+always @(*) begin
+    L14 = 6'b000_000;
+
+    if(sum == 4'd0) begin
+        L14 = 6'b000_000;
+    end
+    else if(sum == 4'd1)
+        L14 = 3'b01;
+    else if(sum == 4'd2)
+        L14 = 3'b10;
+    else if(sum == 4'd3)
+        L14 = 3'b11;
+
+end
+
+
+endmodule