verilog
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gowin/fpga_project/impl/gwsynthesis/fpga_project_syn.rpt.html
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gowin/fpga_project/impl/gwsynthesis/fpga_project_syn.rpt.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<html>
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<head>
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<title>synthesis Report</title>
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<style type="text/css">
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body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
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div#main_wrapper{ width: 100%; }
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div#content { margin-left: 350px; margin-right: 30px; }
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div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
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div#catalog ul { list-style-type: none; }
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div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
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div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
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div#catalog a:visited { color: #0084ff; }
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div#catalog a:hover { color: #fff; background: #0084ff; }
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hr { margin-top: 30px; margin-bottom: 30px; }
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h1, h3 { text-align: center; }
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h1 {margin-top: 50px; }
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table, th, td { border: 1px solid #aaa; }
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table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
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th, td { padding: 5px 5px 5px 5px; }
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th { color: #fff; font-weight: bold; background-color: #0084ff; }
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table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
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table.detail_table td.label { min-width: 100px; width: 8%;}
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</style>
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</head>
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<body>
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<div id="main_wrapper">
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<div id="catalog_wrapper">
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<div id="catalog">
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<ul>
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<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
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<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
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<li><a href="#resource" style=" font-size: 16px;">Resource</a>
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<ul>
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<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
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<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
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</ul>
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</li>
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</ul>
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</div><!-- catalog -->
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</div><!-- catalog_wrapper -->
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<div id="content">
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<h1><a name="about">Synthesis Messages</a></h1>
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<table class="summary_table">
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<tr>
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<td class="label">Report Title</td>
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<td>GowinSynthesis Report</td>
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</tr>
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<tr>
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<td class="label">Design File</td>
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<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v<br>
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\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v<br>
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\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v<br>
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\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v<br>
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</td>
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</tr>
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<tr>
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<td class="label">GowinSynthesis Constraints File</td>
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<td>---</td>
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</tr>
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<tr>
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<td class="label">Tool Version</td>
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<td>V1.9.9.03 Education (64-bit)</td>
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</tr>
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<tr>
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<td class="label">Part Number</td>
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<td>GW2A-LV18PG256C8/I7</td>
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</tr>
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<tr>
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<td class="label">Device</td>
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<td>GW2A-18</td>
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</tr>
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<tr>
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<td class="label">Device Version</td>
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<td>C</td>
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</tr>
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<tr>
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<td class="label">Created Time</td>
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<td>Fri Jul 5 01:47:50 2024
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</td>
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</tr>
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<tr>
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<td class="label">Legal Announcement</td>
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<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
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</tr>
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</table>
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<h1><a name="summary">Synthesis Details</a></h1>
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<table class="summary_table">
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<tr>
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<td class="label">Top Level Module</td>
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<td>ledTest</td>
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</tr>
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<tr>
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<td class="label">Synthesis Process</td>
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<td>Running parser:<br/> CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.256s, Peak memory usage = 438.125MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 438.125MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 438.125MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 438.125MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 438.125MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 438.125MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.381s, Peak memory usage = 438.125MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/>Generate output files:<br/> CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 438.125MB<br/></td>
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</tr>
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<tr>
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<td class="label">Total Time and Memory Usage</td>
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<td>CPU time = 0h 0m 0.201s, Elapsed time = 0h 0m 0.729s, Peak memory usage = 438.125MB</td>
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</tr>
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</table>
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<h1><a name="resource">Resource</a></h1>
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<h2><a name="usage">Resource Usage Summary</a></h2>
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<table class="summary_table">
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<tr>
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<td class="label"><b>Resource</b></td>
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<td><b>Usage</b></td>
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</tr>
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<tr>
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<td class="label"><b>I/O Port </b></td>
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<td>7</td>
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</tr>
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<tr>
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<td class="label"><b>I/O Buf </b></td>
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<td>7</td>
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</tr>
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<tr>
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<td class="label">    IBUF</td>
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<td>4</td>
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</tr>
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<tr>
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<td class="label">    OBUF</td>
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<td>3</td>
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</tr>
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<tr>
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<td class="label"><b>LUT </b></td>
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<td>2</td>
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</tr>
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<tr>
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<td class="label">    LUT4</td>
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<td>2</td>
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</tr>
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</table>
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<h2><a name="utilization">Resource Utilization Summary</a></h2>
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<table class="summary_table">
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<tr>
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<td class="label"><b>Resource</b></td>
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<td><b>Usage</b></td>
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<td><b>Utilization</b></td>
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</tr>
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<tr>
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<td class="label">Logic</td>
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<td>2(2 LUT, 0 ALU) / 20736</td>
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<td><1%</td>
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</tr>
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<tr>
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<td class="label">Register</td>
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<td>0 / 16173</td>
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<td>0%</td>
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</tr>
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<tr>
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<td class="label">  --Register as Latch</td>
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<td>0 / 16173</td>
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<td>0%</td>
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</tr>
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<tr>
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<td class="label">  --Register as FF</td>
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<td>0 / 16173</td>
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<td>0%</td>
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</tr>
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<tr>
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<td class="label">BSRAM</td>
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<td>0 / 46</td>
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<td>0%</td>
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</tr>
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</table>
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</div><!-- content -->
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</div><!-- main_wrapper -->
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</body>
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</html>
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