verilog

2024-07-05 19:15:16 +03:00
parent 492a55d360
commit c1f0851a45
136 changed files with 11599 additions and 0 deletions
--- a/gowin/fpga_project/impl/gwsynthesis/fpga_project.log
+++ b/gowin/fpga_project/impl/gwsynthesis/fpga_project.log
@@ -0,0 +1,38 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v'
+Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v'
+Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v'
+Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v'
+Compiling module 'ledTest'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v":1)
+Compiling module 'bit3adder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":1)
+Compiling module 'halfadder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v":1)
+Compiling module 'fulladder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":1)
+NOTE  (EX0101) : Current top module is "ledTest"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+WARN  (NL0002) : The module "bit3adder" instantiated to "adder" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v":12)
+WARN  (NL0002) : The module "fulladder" instantiated to "fa0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":10)
+WARN  (NL0002) : The module "halfadder" instantiated to "ha1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":8)
+WARN  (NL0002) : The module "halfadder" instantiated to "ha2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":9)
+WARN  (NL0002) : The module "fulladder" instantiated to "fa1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":11)
+WARN  (NL0002) : The module "halfadder" instantiated to "ha1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":8)
+WARN  (NL0002) : The module "halfadder" instantiated to "ha2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":9)
+WARN  (NL0002) : The module "halfadder" instantiated to "ha0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":9)
+[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg" completed
+[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project_syn.rpt.html" completed
+GowinSynthesis finish
--- a/gowin/fpga_project/impl/gwsynthesis/fpga_project.prj
+++ b/gowin/fpga_project/impl/gwsynthesis/fpga_project.prj
@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
+    <FileList>
+        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v" type="verilog"/>
+        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v" type="verilog"/>
+        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v" type="verilog"/>
+        <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="0"/>
+        <Option type="global_freq" value="100.000"/>
+        <Option type="looplimit" value="2000"/>
+        <Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg"/>
+        <Option type="print_all_synthesis_warning" value="0"/>
+        <Option type="ram_rw_check" value="0"/>
+        <Option type="verilog_language" value="verilog-2001"/>
+        <Option type="vhdl_language" value="vhdl-1993"/>
+    </OptionList>
+</Project>
--- a/gowin/fpga_project/impl/gwsynthesis/fpga_project.vg
+++ b/gowin/fpga_project/impl/gwsynthesis/fpga_project.vg
@@ -0,0 +1,50 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.03 Education (64-bit)"
+//Fri Jul  5 01:47:50 2024
+
+//Source file index table:
+//file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v"
+//file1 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v"
+//file2 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v"
+//file3 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v"
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=1008)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+lXyKrsvDMaWe3WBOg3nGgQCt6UWBb5v7Nj/6FwYmUkIpltrnBCtP
+`pragma protect end_protected
--- a/gowin/fpga_project/impl/gwsynthesis/fpga_project_syn.rpt.html
+++ b/gowin/fpga_project/impl/gwsynthesis/fpga_project_syn.rpt.html
@@ -0,0 +1,170 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>synthesis Report</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
+div#main_wrapper{ width: 100%; }
+div#content { margin-left: 350px; margin-right: 30px; }
+div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
+div#catalog ul { list-style-type: none; }
+div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
+div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
+div#catalog a:visited { color: #0084ff; }
+div#catalog a:hover { color: #fff; background: #0084ff; }
+hr { margin-top: 30px; margin-bottom: 30px; }
+h1, h3 { text-align: center; }
+h1 {margin-top: 50px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { padding: 5px 5px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
+table.detail_table td.label { min-width: 100px; width: 8%;}
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="catalog_wrapper">
+<div id="catalog">
+<ul>
+<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
+<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
+<li><a href="#resource" style=" font-size: 16px;">Resource</a>
+<ul>
+<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
+<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
+</ul>
+</li>
+</ul>
+</div><!-- catalog -->
+</div><!-- catalog_wrapper -->
+<div id="content">
+<h1><a name="about">Synthesis Messages</a></h1>
+<table class="summary_table">
+<tr>
+<td class="label">Report Title</td>
+<td>GowinSynthesis Report</td>
+</tr>
+<tr>
+<td class="label">Design File</td>
+<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v<br>
+\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v<br>
+\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v<br>
+\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v<br>
+</td>
+</tr>
+<tr>
+<td class="label">GowinSynthesis Constraints File</td>
+<td>---</td>
+</tr>
+<tr>
+<td class="label">Tool Version</td>
+<td>V1.9.9.03 Education (64-bit)</td>
+</tr>
+<tr>
+<td class="label">Part Number</td>
+<td>GW2A-LV18PG256C8/I7</td>
+</tr>
+<tr>
+<td class="label">Device</td>
+<td>GW2A-18</td>
+</tr>
+<tr>
+<td class="label">Device Version</td>
+<td>C</td>
+</tr>
+<tr>
+<td class="label">Created Time</td>
+<td>Fri Jul  5 01:47:50 2024
+</td>
+</tr>
+<tr>
+<td class="label">Legal Announcement</td>
+<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
+</tr>
+</table>
+<h1><a name="summary">Synthesis Details</a></h1>
+<table class="summary_table">
+<tr>
+<td class="label">Top Level Module</td>
+<td>ledTest</td>
+</tr>
+<tr>
+<td class="label">Synthesis Process</td>
+<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.256s, Peak memory usage = 438.125MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.381s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 438.125MB<br/></td>
+</tr>
+<tr>
+<td class="label">Total Time and Memory Usage</td>
+<td>CPU time = 0h 0m 0.201s, Elapsed time = 0h 0m 0.729s, Peak memory usage = 438.125MB</td>
+</tr>
+</table>
+<h1><a name="resource">Resource</a></h1>
+<h2><a name="usage">Resource Usage Summary</a></h2>
+<table class="summary_table">
+<tr>
+<td class="label"><b>Resource</b></td>
+<td><b>Usage</b></td>
+</tr>
+<tr>
+<td class="label"><b>I/O Port </b></td>
+<td>7</td>
+</tr>
+<tr>
+<td class="label"><b>I/O Buf </b></td>
+<td>7</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
+<td>4</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
+<td>3</td>
+</tr>
+<tr>
+<td class="label"><b>LUT </b></td>
+<td>2</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
+<td>2</td>
+</tr>
+</table>
+<h2><a name="utilization">Resource Utilization Summary</a></h2>
+<table class="summary_table">
+<tr>
+<td class="label"><b>Resource</b></td>
+<td><b>Usage</b></td>
+<td><b>Utilization</b></td>
+</tr>
+<tr>
+<td class="label">Logic</td>
+<td>2(2 LUT, 0 ALU) / 20736</td>
+<td><1%</td>
+</tr>
+<tr>
+<td class="label">Register</td>
+<td>0 / 16173</td>
+<td>0%</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp--Register as Latch</td>
+<td>0 / 16173</td>
+<td>0%</td>
+</tr>
+<tr>
+<td class="label">&nbsp&nbsp--Register as FF</td>
+<td>0 / 16173</td>
+<td>0%</td>
+</tr>
+<tr>
+<td class="label">BSRAM</td>
+<td>0 / 46</td>
+<td>0%</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>
--- a/gowin/fpga_project/impl/gwsynthesis/fpga_project_syn_resource.html
+++ b/gowin/fpga_project/impl/gwsynthesis/fpga_project_syn_resource.html
@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">ledTest (//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v)</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">2</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>
--- a/gowin/fpga_project/impl/gwsynthesis/fpga_project_syn_rsc.xml
+++ b/gowin/fpga_project/impl/gwsynthesis/fpga_project_syn_rsc.xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="ledTest" Lut="2" T_Lut="2(2)"/>