From a69386c7b4e78c260fcc0cfa3cd31f0de521fffb Mon Sep 17 00:00:00 2001 From: k0rrluna Date: Sun, 1 Dec 2024 13:42:54 +0300 Subject: [PATCH] nand2Tetris --- iverilog/nand2tetris/nands/andGate | 57 ++++++++++++++++++++++++++ iverilog/nand2tetris/nands/andGate.v | 16 ++++++++ iverilog/nand2tetris/nands/andGate.vcd | 38 +++++++++++++++++ iverilog/nand2tetris/nands/andGateTB.v | 29 +++++++++++++ iverilog/nand2tetris/nands/notGate | 39 ++++++++++++++++++ iverilog/nand2tetris/nands/notGate.v | 5 +++ iverilog/nand2tetris/nands/notGate.vcd | 27 ++++++++++++ iverilog/nand2tetris/nands/notGateTB.v | 20 +++++++++ iverilog/nand2tetris/nands/orGate.v | 13 ++++++ iverilog/nand2tetris/nands/orGateTB.v | 0 iverilog/tobb/lab2/Fulladder.v | 26 ++++++++++++ iverilog/tobb/lab2/fulladder.v | 13 ------ iverilog/tobb/lab2/fulladdertb.v | 4 +- iverilog/tobb/lab2/halfaddertb.v | 4 +- 14 files changed, 274 insertions(+), 17 deletions(-) create mode 100644 iverilog/nand2tetris/nands/andGate create mode 100644 iverilog/nand2tetris/nands/andGate.v create mode 100644 iverilog/nand2tetris/nands/andGate.vcd create mode 100644 iverilog/nand2tetris/nands/andGateTB.v create mode 100644 iverilog/nand2tetris/nands/notGate create mode 100644 iverilog/nand2tetris/nands/notGate.v create mode 100644 iverilog/nand2tetris/nands/notGate.vcd create mode 100644 iverilog/nand2tetris/nands/notGateTB.v create mode 100644 iverilog/nand2tetris/nands/orGate.v create mode 100644 iverilog/nand2tetris/nands/orGateTB.v create mode 100644 iverilog/tobb/lab2/Fulladder.v delete mode 100644 iverilog/tobb/lab2/fulladder.v diff --git a/iverilog/nand2tetris/nands/andGate b/iverilog/nand2tetris/nands/andGate new file mode 100644 index 0000000..a369d12 --- /dev/null +++ b/iverilog/nand2tetris/nands/andGate @@ -0,0 +1,57 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +S_0x55a27af99200 .scope module, "andGateTB" "andGateTB" 2 1; + .timescale 0 0; +v0x55a27afaa010_0 .var "A", 0 0; +v0x55a27afaa0e0_0 .var "B", 0 0; +v0x55a27afaa1b0_0 .net "Y", 0 0, L_0x55a27afaa3f0; 1 drivers +S_0x55a27af99390 .scope module, "uut" "andGate" 2 5, 3 1 0, S_0x55a27af99200; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /INPUT 1 "B"; + .port_info 2 /OUTPUT 1 "Y"; +L_0x55a27afaa2b0 .functor NAND 1, v0x55a27afaa010_0, v0x55a27afaa0e0_0, C4<1>, C4<1>; +L_0x55a27afaa3f0 .functor NAND 1, L_0x55a27afaa2b0, L_0x55a27afaa2b0, C4<1>, C4<1>; +v0x55a27af61c00_0 .net "A", 0 0, v0x55a27afaa010_0; 1 drivers +v0x55a27afa9d70_0 .net "B", 0 0, v0x55a27afaa0e0_0; 1 drivers +v0x55a27afa9e30_0 .net "Y", 0 0, L_0x55a27afaa3f0; alias, 1 drivers +v0x55a27afa9ed0_0 .net "tempOut", 0 0, L_0x55a27afaa2b0; 1 drivers + .scope S_0x55a27af99200; +T_0 ; + %vpi_call 2 12 "$dumpfile", "andGate.vcd" {0 0 0}; + %vpi_call 2 13 "$dumpvars" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55a27afaa010_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55a27afaa0e0_0, 0, 1; + %delay 10, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55a27afaa010_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x55a27afaa0e0_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x55a27afaa010_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55a27afaa0e0_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x55a27afaa010_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x55a27afaa0e0_0, 0, 1; + %delay 10, 0; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "andGateTB.v"; + "andGate.v"; diff --git a/iverilog/nand2tetris/nands/andGate.v b/iverilog/nand2tetris/nands/andGate.v new file mode 100644 index 0000000..7ae875c --- /dev/null +++ b/iverilog/nand2tetris/nands/andGate.v @@ -0,0 +1,16 @@ + +module andGate ( + input wire A_i, + input wire B_i, + output wire Y_o +); + + + wire nand_out; + + + nand nand1 (nand_out, A_i, B_i); + + nand nand2 (Y_o, nand_out, nand_out); + +endmodule diff --git a/iverilog/nand2tetris/nands/andGate.vcd b/iverilog/nand2tetris/nands/andGate.vcd new file mode 100644 index 0000000..d79ff86 --- /dev/null +++ b/iverilog/nand2tetris/nands/andGate.vcd @@ -0,0 +1,38 @@ +$date + Sun Dec 1 02:41:57 2024 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module andGateTB $end +$var wire 1 ! Y $end +$var reg 1 " A $end +$var reg 1 # B $end +$scope module uut $end +$var wire 1 " A $end +$var wire 1 # B $end +$var wire 1 ! Y $end +$var wire 1 $ tempOut $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +1$ +0# +0" +0! +$end +#10 +1# +#20 +0# +1" +#30 +1! +0$ +1# +#40 diff --git a/iverilog/nand2tetris/nands/andGateTB.v b/iverilog/nand2tetris/nands/andGateTB.v new file mode 100644 index 0000000..1eee548 --- /dev/null +++ b/iverilog/nand2tetris/nands/andGateTB.v @@ -0,0 +1,29 @@ +module andGateTB (); + reg A, B; + wire Y; + + andGate uut ( + .A(A), + .B(B), + .Y(Y) + ); + + initial begin + $dumpfile("andGate.vcd"); + $dumpvars; + A = 1'b0; + B = 1'b0; + #10; + A = 1'b0; + B = 1'b1; + #10; + A = 1'b1; + B = 1'b0; + #10; + A = 1'b1; + B = 1'b1; + #10; + $finish; + end + +endmodule diff --git a/iverilog/nand2tetris/nands/notGate b/iverilog/nand2tetris/nands/notGate new file mode 100644 index 0000000..9b040a9 --- /dev/null +++ b/iverilog/nand2tetris/nands/notGate @@ -0,0 +1,39 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +S_0x5628fffa0b60 .scope module, "notGateTB" "notGateTB" 2 1; + .timescale 0 0; +v0x5628fffafdd0_0 .var "A", 0 0; +v0x5628fffafe70_0 .net "B", 0 0, L_0x5628fffaff40; 1 drivers +S_0x5628fffa0cf0 .scope module, "uut" "notGate" 2 6, 3 1 0, S_0x5628fffa0b60; + .timescale 0 0; + .port_info 0 /INPUT 1 "A"; + .port_info 1 /OUTPUT 1 "B"; +L_0x5628fffaff40 .functor NAND 1, v0x5628fffafdd0_0, v0x5628fffafdd0_0, C4<1>, C4<1>; +v0x5628fff697f0_0 .net "A", 0 0, v0x5628fffafdd0_0; 1 drivers +v0x5628fff69c00_0 .net "B", 0 0, L_0x5628fffaff40; alias, 1 drivers + .scope S_0x5628fffa0b60; +T_0 ; + %vpi_call 2 12 "$dumpfile", "notGate.vcd" {0 0 0}; + %vpi_call 2 13 "$dumpvars" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x5628fffafdd0_0, 0, 1; + %delay 10, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x5628fffafdd0_0, 0, 1; + %delay 10, 0; + %vpi_call 2 18 "$finish" {0 0 0}; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "notGateTB.v"; + "notGate.v"; diff --git a/iverilog/nand2tetris/nands/notGate.v b/iverilog/nand2tetris/nands/notGate.v new file mode 100644 index 0000000..1117bce --- /dev/null +++ b/iverilog/nand2tetris/nands/notGate.v @@ -0,0 +1,5 @@ +module notGate (input A, + output B); + + nand nand1 (B, A, A); +endmodule diff --git a/iverilog/nand2tetris/nands/notGate.vcd b/iverilog/nand2tetris/nands/notGate.vcd new file mode 100644 index 0000000..c027be1 --- /dev/null +++ b/iverilog/nand2tetris/nands/notGate.vcd @@ -0,0 +1,27 @@ +$date + Sun Dec 1 02:50:52 2024 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module notGateTB $end +$var wire 1 ! B $end +$var reg 1 " A $end +$scope module uut $end +$var wire 1 " A $end +$var wire 1 ! B $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0" +1! +$end +#10 +0! +1" +#20 diff --git a/iverilog/nand2tetris/nands/notGateTB.v b/iverilog/nand2tetris/nands/notGateTB.v new file mode 100644 index 0000000..b0e3955 --- /dev/null +++ b/iverilog/nand2tetris/nands/notGateTB.v @@ -0,0 +1,20 @@ +module notGateTB (); + + reg A; + wire B; + + notGate uut ( + .A(A), + .B(B) + ); + + initial begin + $dumpfile("notGate.vcd"); + $dumpvars; + A = 1'b0; + #10; + A = 1'b1; + #10; + $finish; + end +endmodule diff --git a/iverilog/nand2tetris/nands/orGate.v b/iverilog/nand2tetris/nands/orGate.v new file mode 100644 index 0000000..7d9805d --- /dev/null +++ b/iverilog/nand2tetris/nands/orGate.v @@ -0,0 +1,13 @@ +module orGate ( + input A_i, + input B_i, + output F_o +); + +wire nand1_out, nand2_out; + +nand nand1(nand1_out, A_i, A_i); +nand nand2(nand2_out, B_i, B_i); +nand nand3(F_o, nand1_out, nand2_out); + +endmodule diff --git a/iverilog/nand2tetris/nands/orGateTB.v b/iverilog/nand2tetris/nands/orGateTB.v new file mode 100644 index 0000000..e69de29 diff --git a/iverilog/tobb/lab2/Fulladder.v b/iverilog/tobb/lab2/Fulladder.v new file mode 100644 index 0000000..bf3d744 --- /dev/null +++ b/iverilog/tobb/lab2/Fulladder.v @@ -0,0 +1,26 @@ +module Fulladder ( + input A, + input B, + input Cin, + output S, + output Cout +); + wire AxB, AnB1, AnB2; + + + halfadder h1 ( + .A(A), + .B(B), + .Sum(AxB), + .Carry(AnB2) + ); + + halfadder h2 ( + .A(AxB), + .B(Cin), + .Sum(S), + .Carry(AnB1) + ); + + or o1 (.Y(Cout), .A(AnB1), .B(AnB2)); +endmodule diff --git a/iverilog/tobb/lab2/fulladder.v b/iverilog/tobb/lab2/fulladder.v deleted file mode 100644 index 70f7bf7..0000000 --- a/iverilog/tobb/lab2/fulladder.v +++ /dev/null @@ -1,13 +0,0 @@ -module fullAdder ( - input A, - input B, - input Cin, - output S, - output Cout -); - wire AxB, AnB1, AnB2; - halfadder h1(A, B, AxB, AnB2); - halfadder h2(AxB, Cin, S, AnB1); - - or o1(Cout, AnB1, AnB2); -endmodule \ No newline at end of file diff --git a/iverilog/tobb/lab2/fulladdertb.v b/iverilog/tobb/lab2/fulladdertb.v index 97ed83b..87b9622 100644 --- a/iverilog/tobb/lab2/fulladdertb.v +++ b/iverilog/tobb/lab2/fulladdertb.v @@ -3,7 +3,7 @@ module fulladdertb (); reg r1, r2, r3; wire w1, w2; -fullAdder uut( +FullAdder uut( .A(r1), .B(r2), .Cin(r3), @@ -26,4 +26,4 @@ initial begin $display(w2); end -endmodule \ No newline at end of file +endmodule diff --git a/iverilog/tobb/lab2/halfaddertb.v b/iverilog/tobb/lab2/halfaddertb.v index 501c067..14a73f1 100644 --- a/iverilog/tobb/lab2/halfaddertb.v +++ b/iverilog/tobb/lab2/halfaddertb.v @@ -14,5 +14,5 @@ initial begin A = 1'b1; B = 1'b0; #10; A = 1'b1; B = 1'b1; #10; end - -endmodule \ No newline at end of file + +endmodule