kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

tangFpga

Browse Source
This commit is contained in:
k0rrluna
2025-01-20 18:23:08 +03:00
parent a007343feb
commit 8e613a767e
19 changed files with 1158 additions and 1012 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
gowin/bttn/impl/temp/rtl_parser.result
View File

@ -9,7 +9,7 @@
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 10,
"InstLine" : 11,
"InstName" : "a1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"ModuleLine" : 1,
@ -691,7 +691,7 @@
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 11,
"InstLine" : 12,
"InstName" : "s1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v",
"ModuleLine" : 1,