tangFpga
This commit is contained in:
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@ -25,5 +25,5 @@ Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pn
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Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.html" completed
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Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.txt" completed
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Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.tr.html" completed
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Sat Jan 18 22:12:46 2025
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Mon Jan 20 17:48:16 2025
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@ -78,7 +78,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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</tr>
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<tr>
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<td class="label">Created Time</td>
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<td>Sat Jan 18 22:12:42 2025
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<td>Mon Jan 20 17:48:13 2025
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</td>
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</tr>
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<tr>
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@ -342,6 +342,60 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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<td>1.8</td>
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||||
</tr>
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||||
<tr>
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<td class="label">Cin</td>
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||||
<td></td>
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||||
<td>E9/6</td>
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<td>Y</td>
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<td>in</td>
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||||
<td>IOL38[B]</td>
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||||
<td>LVCMOS18</td>
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||||
<td>NA</td>
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||||
<td>UP</td>
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||||
<td>ON</td>
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||||
<td>NONE</td>
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||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>OFF</td>
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||||
<td>NA</td>
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||||
<td>1.8</td>
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</tr>
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<tr>
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<td class="label">leds[0]</td>
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||||
<td></td>
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<td>L16/1</td>
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<td>Y</td>
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||||
<td>out</td>
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||||
<td>IOT34[A]</td>
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||||
<td>LVCMOS18</td>
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||||
<td>8</td>
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||||
<td>NONE</td>
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||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>OFF</td>
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||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>1.8</td>
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||||
</tr>
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||||
<tr>
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||||
<td class="label">leds[1]</td>
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||||
<td></td>
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||||
<td>L14/1</td>
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||||
<td>Y</td>
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||||
<td>out</td>
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||||
<td>IOT34[B]</td>
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||||
<td>LVCMOS18</td>
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||||
<td>8</td>
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||||
<td>NONE</td>
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||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>OFF</td>
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||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>1.8</td>
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</tr>
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<tr>
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<td class="label">Y[0]</td>
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<td></td>
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<td>P6/3</td>
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@ -1107,32 +1161,32 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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</tr>
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<tr>
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<td class="label">L16/1</td>
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<td>-</td>
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<td>in</td>
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<td>leds[0]</td>
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<td>out</td>
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<td>IOT34[A]</td>
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||||
<td>LVCMOS18</td>
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||||
<td>NA</td>
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||||
<td>UP</td>
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||||
<td>ON</td>
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||||
<td>8</td>
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||||
<td>NONE</td>
|
||||
<td>NA</td>
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||||
<td>NA</td>
|
||||
<td>OFF</td>
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||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>1.8</td>
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||||
</tr>
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||||
<tr>
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||||
<td class="label">L14/1</td>
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||||
<td>-</td>
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<td>in</td>
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||||
<td>leds[1]</td>
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||||
<td>out</td>
|
||||
<td>IOT34[B]</td>
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||||
<td>LVCMOS18</td>
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||||
<td>NA</td>
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||||
<td>UP</td>
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||||
<td>ON</td>
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||||
<td>8</td>
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||||
<td>NONE</td>
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||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>OFF</td>
|
||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>NA</td>
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||||
<td>1.8</td>
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||||
@ -2915,7 +2969,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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</tr>
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<tr>
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<td class="label">E9/6</td>
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<td>-</td>
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<td>Cin</td>
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<td>in</td>
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<td>IOL38[B]</td>
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<td>LVCMOS18</td>
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@ -2925,7 +2979,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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<td>NONE</td>
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<td>NA</td>
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<td>NA</td>
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||||
<td>NA</td>
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||||
<td>OFF</td>
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||||
<td>NA</td>
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||||
<td>1.8</td>
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||||
</tr>
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||||
|
@ -89,7 +89,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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</tr>
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<tr>
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<td class="label">Created Time</td>
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<td>Sat Jan 18 22:12:42 2025
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<td>Mon Jan 20 17:48:13 2025
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</td>
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</tr>
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<tr>
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@ -161,22 +161,22 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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<table class="summary_table">
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<tr>
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<td class="label">Total Power (mW)</td>
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<td>124.284</td>
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<td>124.522</td>
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</tr>
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<tr>
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<td class="label">Quiescent Power (mW)</td>
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<td>121.171</td>
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<td>121.169</td>
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</tr>
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<tr>
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<td class="label">Dynamic Power (mW)</td>
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<td>3.114</td>
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<td>3.353</td>
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</tr>
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</table>
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<h2><a name="Thermal_Info">Thermal Information:</a></h2>
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<table class="summary_table">
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<tr>
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<td class="label">Junction Temperature</td>
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<td>28.980</td>
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<td>28.987</td>
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</tr>
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<tr>
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<td class="label">Theta JA</td>
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@ -184,7 +184,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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</tr>
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<tr>
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<td class="label">Max Allowed Ambient Temperature</td>
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<td>81.020</td>
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<td>81.013</td>
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</tr>
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</table>
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<h2><a name="Supply_Summary">Supply Information:</a></h2>
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@ -199,23 +199,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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<tr>
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<td>VCC</td>
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<td>1.000</td>
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<td>0.513</td>
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<td>69.983</td>
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||||
<td>70.496</td>
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||||
<td>0.552</td>
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||||
<td>69.981</td>
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||||
<td>70.533</td>
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||||
</tr>
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<tr>
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<td>VCCX</td>
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||||
<td>3.300</td>
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||||
<td>0.513</td>
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||||
<td>0.552</td>
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||||
<td>15.000</td>
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||||
<td>51.192</td>
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||||
<td>51.322</td>
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</tr>
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<tr>
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<td>VCCIO18</td>
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<td>1.800</td>
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||||
<td>0.505</td>
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<td>0.937</td>
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<td>2.597</td>
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<td>0.544</td>
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<td>0.938</td>
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<td>2.668</td>
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</tr>
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</table>
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<h1><a name="Detail">Power Details</a></h1>
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@ -229,9 +229,9 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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</tr>
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<tr>
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<td>IO</td>
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||||
<td>7.854
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<td>4.740
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<td>6.500
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<td>8.544
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<td>5.191
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<td>6.250
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||||
</tr>
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</table>
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<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
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|
@ -83,7 +83,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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||||
</tr>
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||||
<tr>
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||||
<td class="label">Created Time</td>
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<td>Sat Jan 18 22:12:44 2025
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||||
<td>Mon Jan 20 17:48:14 2025
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||||
</td>
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||||
</tr>
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||||
<tr>
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||||
@ -97,24 +97,24 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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||||
<tr>
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||||
<td class="label">Place & Route Process</td>
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||||
<td>Running placement:
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||||
Placement Phase 0: CPU time = 0h 0m 0.021s, Elapsed time = 0h 0m 0.021s
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||||
Placement Phase 1: CPU time = 0h 0m 0.354s, Elapsed time = 0h 0m 0.354s
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||||
Placement Phase 2: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s
|
||||
Placement Phase 0: CPU time = 0h 0m 0.024s, Elapsed time = 0h 0m 0.024s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.348s, Elapsed time = 0h 0m 0.348s
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||||
Placement Phase 2: CPU time = 0h 0m 0.009s, Elapsed time = 0h 0m 0.009s
|
||||
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
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||||
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
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||||
Running routing:
|
||||
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.173s, Elapsed time = 0h 0m 0.173s
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||||
Routing Phase 2: CPU time = 0h 0m 0.224s, Elapsed time = 0h 0m 0.224s
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||||
Routing Phase 2: CPU time = 0h 0m 0.232s, Elapsed time = 0h 0m 0.231s
|
||||
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Total Routing: CPU time = 0h 0m 0.397s, Elapsed time = 0h 0m 0.397s
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||||
Total Routing: CPU time = 0h 0m 0.405s, Elapsed time = 0h 0m 0.404s
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||||
Generate output files:
|
||||
CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s
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||||
</td>
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||||
</tr>
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||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
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||||
<td>CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 391MB</td>
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||||
<td>CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 443MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<br/>
|
||||
@ -129,12 +129,12 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>137/20736</td>
|
||||
<td>141/20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    --LUT,ALU,ROM16</td>
|
||||
<td>137(137 LUT, 0 ALU, 0 ROM16)</td>
|
||||
<td>141(141 LUT, 0 ALU, 0 ROM16)</td>
|
||||
<td>-</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -169,27 +169,27 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">CLS</td>
|
||||
<td>74/10368</td>
|
||||
<td>75/10368</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">I/O Port</td>
|
||||
<td>25</td>
|
||||
<td>28</td>
|
||||
<td>-</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">I/O Buf</td>
|
||||
<td>25</td>
|
||||
<td>28</td>
|
||||
<td>-</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">     --Input Buf</td>
|
||||
<td>13</td>
|
||||
<td>14</td>
|
||||
<td>-</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">     --Output Buf</td>
|
||||
<td>12</td>
|
||||
<td>14</td>
|
||||
<td>-</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -264,7 +264,7 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">bank 1</td>
|
||||
<td>3/20(15%)</td>
|
||||
<td>5/20(25%)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">bank 2</td>
|
||||
@ -284,7 +284,7 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">bank 6</td>
|
||||
<td>1/18(5%)</td>
|
||||
<td>2/18(11%)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">bank 7</td>
|
||||
@ -588,6 +588,60 @@ Generate output files:
|
||||
<td>1.8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Cin</td>
|
||||
<td></td>
|
||||
<td>E9/6</td>
|
||||
<td>Y</td>
|
||||
<td>in</td>
|
||||
<td>IOL38[B]</td>
|
||||
<td>LVCMOS18</td>
|
||||
<td>NA</td>
|
||||
<td>UP</td>
|
||||
<td>ON</td>
|
||||
<td>NONE</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>OFF</td>
|
||||
<td>NA</td>
|
||||
<td>1.8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">leds[0]</td>
|
||||
<td></td>
|
||||
<td>L16/1</td>
|
||||
<td>Y</td>
|
||||
<td>out</td>
|
||||
<td>IOT34[A]</td>
|
||||
<td>LVCMOS18</td>
|
||||
<td>8</td>
|
||||
<td>NONE</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>OFF</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>1.8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">leds[1]</td>
|
||||
<td></td>
|
||||
<td>L14/1</td>
|
||||
<td>Y</td>
|
||||
<td>out</td>
|
||||
<td>IOT34[B]</td>
|
||||
<td>LVCMOS18</td>
|
||||
<td>8</td>
|
||||
<td>NONE</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>OFF</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>1.8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Y[0]</td>
|
||||
<td></td>
|
||||
<td>P6/3</td>
|
||||
@ -1353,32 +1407,32 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">L16/1</td>
|
||||
<td>-</td>
|
||||
<td>in</td>
|
||||
<td>leds[0]</td>
|
||||
<td>out</td>
|
||||
<td>IOT34[A]</td>
|
||||
<td>LVCMOS18</td>
|
||||
<td>NA</td>
|
||||
<td>UP</td>
|
||||
<td>ON</td>
|
||||
<td>8</td>
|
||||
<td>NONE</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>OFF</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>1.8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">L14/1</td>
|
||||
<td>-</td>
|
||||
<td>in</td>
|
||||
<td>leds[1]</td>
|
||||
<td>out</td>
|
||||
<td>IOT34[B]</td>
|
||||
<td>LVCMOS18</td>
|
||||
<td>NA</td>
|
||||
<td>UP</td>
|
||||
<td>ON</td>
|
||||
<td>8</td>
|
||||
<td>NONE</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>OFF</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>1.8</td>
|
||||
@ -3161,7 +3215,7 @@ Generate output files:
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">E9/6</td>
|
||||
<td>-</td>
|
||||
<td>Cin</td>
|
||||
<td>in</td>
|
||||
<td>IOL38[B]</td>
|
||||
<td>LVCMOS18</td>
|
||||
@ -3171,7 +3225,7 @@ Generate output files:
|
||||
<td>NONE</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>NA</td>
|
||||
<td>OFF</td>
|
||||
<td>NA</td>
|
||||
<td>1.8</td>
|
||||
</tr>
|
||||
|
@ -12,27 +12,27 @@
|
||||
<Part Number>: GW2A-LV18PG256C8/I7
|
||||
<Device>: GW2A-18
|
||||
<Device Version>: C
|
||||
<Created Time>:Sat Jan 18 22:12:45 2025
|
||||
<Created Time>:Mon Jan 20 17:48:15 2025
|
||||
|
||||
|
||||
2. PnR Details
|
||||
|
||||
Running placement:
|
||||
Placement Phase 0: CPU time = 0h 0m 0.021s, Elapsed time = 0h 0m 0.021s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.354s, Elapsed time = 0h 0m 0.354s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s
|
||||
Placement Phase 0: CPU time = 0h 0m 0.024s, Elapsed time = 0h 0m 0.024s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.348s, Elapsed time = 0h 0m 0.348s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.009s, Elapsed time = 0h 0m 0.009s
|
||||
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
|
||||
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
Running routing:
|
||||
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.173s, Elapsed time = 0h 0m 0.173s
|
||||
Routing Phase 2: CPU time = 0h 0m 0.224s, Elapsed time = 0h 0m 0.224s
|
||||
Routing Phase 2: CPU time = 0h 0m 0.232s, Elapsed time = 0h 0m 0.231s
|
||||
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Total Routing: CPU time = 0h 0m 0.397s, Elapsed time = 0h 0m 0.397s
|
||||
Total Routing: CPU time = 0h 0m 0.405s, Elapsed time = 0h 0m 0.404s
|
||||
Generate output files:
|
||||
CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s
|
||||
|
||||
Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 391MB
|
||||
Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 443MB
|
||||
|
||||
|
||||
3. Resource Usage Summary
|
||||
@ -40,19 +40,19 @@
|
||||
----------------------------------------------------------
|
||||
Resources | Usage
|
||||
----------------------------------------------------------
|
||||
Logic | 137/20736 <1%
|
||||
--LUT,ALU,ROM16 | 137(137 LUT, 0 ALU, 0 ROM16)
|
||||
Logic | 141/20736 <1%
|
||||
--LUT,ALU,ROM16 | 141(141 LUT, 0 ALU, 0 ROM16)
|
||||
--SSRAM(RAM16) | 0
|
||||
Register | 0/16173 0%
|
||||
--Logic Register as Latch | 0/15552 0%
|
||||
--Logic Register as FF | 0/15552 0%
|
||||
--I/O Register as Latch | 0/621 0%
|
||||
--I/O Register as FF | 0/621 0%
|
||||
CLS | 74/10368 <1%
|
||||
I/O Port | 25
|
||||
I/O Buf | 25
|
||||
--Input Buf | 13
|
||||
--Output Buf | 12
|
||||
CLS | 75/10368 <1%
|
||||
I/O Port | 28
|
||||
I/O Buf | 28
|
||||
--Input Buf | 14
|
||||
--Output Buf | 14
|
||||
--Inout Buf | 0
|
||||
IOLOGIC | 0%
|
||||
BSRAM | 0%
|
||||
@ -75,12 +75,12 @@
|
||||
I/O Bank | Usage
|
||||
-----------------------
|
||||
bank 0 | 1/29(3%)
|
||||
bank 1 | 3/20(15%)
|
||||
bank 1 | 5/20(25%)
|
||||
bank 2 | 2/20(10%)
|
||||
bank 3 | 8/32(25%)
|
||||
bank 4 | 2/36(5%)
|
||||
bank 5 | 0/36(0%)
|
||||
bank 6 | 1/18(5%)
|
||||
bank 6 | 2/18(11%)
|
||||
bank 7 | 8/16(50%)
|
||||
=======================
|
||||
|
||||
@ -125,6 +125,9 @@ opCodeA[1] | | T4/4 | Y | in | IOB45[B] | LVCMOS
|
||||
opCodeA[2] | | E8/6 | Y | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
select[0] | | A15/7 | Y | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
select[1] | | A14/7 | Y | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
Cin | | E9/6 | Y | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
leds[0] | | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
leds[1] | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
Y[0] | | P6/3 | Y | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
Y[1] | | T7/3 | Y | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
Y[2] | | P8/3 | Y | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
@ -180,8 +183,8 @@ K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON
|
||||
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L16/1 | - | in | IOT34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L14/1 | - | in | IOT34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L16/1 | leds[0] | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
L14/1 | leds[1] | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
@ -295,7 +298,7 @@ A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON
|
||||
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E9/6 | Cin | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
|
@ -55,7 +55,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat Jan 18 22:12:46 2025
|
||||
<td>Mon Jan 20 17:48:16 2025
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@ -76,11 +76,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Paths Analyzed</td>
|
||||
<td>124</td>
|
||||
<td>158</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Endpoints Analyzed</td>
|
||||
<td>12</td>
|
||||
<td>14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Falling Endpoints</td>
|
||||
@ -191,44 +191,44 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
<th class="label">ROUTE CONGESTIONS</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R29C29</td>
|
||||
<td>52.78%</td>
|
||||
<td>R27C30</td>
|
||||
<td>43.06%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R30C29</td>
|
||||
<td>40.28%</td>
|
||||
<td>R29C29</td>
|
||||
<td>43.06%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R27C29</td>
|
||||
<td>40.28%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R26C29</td>
|
||||
<td>33.33%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R30C28</td>
|
||||
<td>33.33%</td>
|
||||
<td>R26C30</td>
|
||||
<td>31.94%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R29C28</td>
|
||||
<td>27.78%</td>
|
||||
<td>30.56%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R29C30</td>
|
||||
<td>27.78%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R30C27</td>
|
||||
<td>26.39%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R29C27</td>
|
||||
<td>23.61%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R30C30</td>
|
||||
<td>19.44%</td>
|
||||
<td>29.17%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R27C28</td>
|
||||
<td>19.44%</td>
|
||||
<td>26.39%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R27C31</td>
|
||||
<td>25.00%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R26C28</td>
|
||||
<td>25.00%</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
|
||||
|
Reference in New Issue
Block a user