overflow fix

2024-12-26 14:51:08 +03:00 · 2024-12-26 14:51:08 +03:00 · 4ca5ab1995
commit 4ca5ab1995
parent fc2c438ec8
4 changed files with 1765 additions and 2004 deletions
--- a/project0.2/ALU
+++ b/project0.2/ALU
--- a/project0.2/ALU.vcd
+++ b/project0.2/ALU.vcd
@ -1,5 +1,5 @@
 $date
-	Mon Dec 23 02:54:24 2024
+	Tue Dec 24 13:48:57 2024
 $end
 $version
 	Icarus Verilog
@ -710,15 +710,15 @@ $upscope $end
 $enddefinitions $end
 #0
 $dumpvars
-b1 j$
-1i$
-1h$
+b1000 j$
+0i$
+0h$
 1g$
-1f$
+0f$
 0e$
-0d$
+1d$
 0c$
-b0 b$
+b11 b$
 0a$
 0`$
 0_$
@ -1037,7 +1037,7 @@ b0 A
 0@
 b0 ?
 b0 >
-b1 =
+b0 =
 b0 <
 b0 ;
 b0 :
@ -1047,7 +1047,7 @@ b0 7
 b0 6
 b0 5
 b0 4
-b1 3
+b1000 3
 b0 2
 b0 1
 b0 0
@ -1056,10 +1056,10 @@ b0 .
 b0 -
 b0 ,
 b0 +
-b0 *
+b11 *
 b0 )
 b0 (
-b0 '
+b11 '
 0&
 b0 %
 b0 $
@ -1068,40 +1068,6 @@ b0 "
 0!
 $end
 #5
-15#
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-b1111 3"
-b1111 -
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-b1111 9
-b1111 7
-b1111 A
 1v
 1""
 1,"
@ -1212,37 +1178,10 @@ b1111 g
 b1111 >#
 b1111 G#
 #15
-15#
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-17#
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-b10101 6
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@ -1251,8 +1190,6 @@ b10101 ;"
 11$
 1|#
 1B$
-b1111 :
-b1111 3"
 1#"
 1<$
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@ -1269,7 +1206,6 @@ b1111 3"
 1M$
 1U$
 1]$
-b1111 -
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@ -1285,7 +1221,6 @@ b111 C$
 1I$
 0Q$
 1Y$
-b1111 +
 1y
 1h#
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@ -1301,7 +1236,6 @@ b1111 +
 1s#
 b1011 y#
 b1101 ?$
-b1111 9
 1!
 bz111 i
 1m
@ -1342,8 +1276,6 @@ b1100 A$
 0W$
 0^$
 1R
-b1111 7
-b1111 A
 1S
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@ -1525,49 +1457,17 @@ b111 g
 b111 >#
 b111 G#
 #25
-1{"
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@ -1581,8 +1481,6 @@ b0 A$
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@ -1599,9 +1497,6 @@ b0 y#
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@ -1636,9 +1531,9 @@ b0 {#
 0+$
 05$
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-b10 =
-b0 7
-b0 A
+0d$
+b10000000 3
+b10000000 j$
 0v
 0K
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@ -1652,9 +1547,8 @@ b0 H
 0~#
 0'$
 0/$
-0i$
-b10 3
-b10 j$
+0g$
+1c$
 bz000 i
 0m
 0N
@ -1692,9 +1586,9 @@ b0 j
 0k
 0t
 0~
-b1 '
-b1 *
-b1 b$
+b111 '
+b111 *
+b111 b$
 0&
 b0 %
 b0 )
@ -1711,40 +1605,6 @@ b0 g
 b0 >#
 b0 G#
 #30
-06#
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-01#
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-0y"
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-b1 :
-b1 3"
-b1 -
-b1 +
-b1 8
-b1 .
-b1 >
 1v
 1""
 1,"
@ -1801,40 +1661,6 @@ b1111 h
 b1111 ?#
 b1111 H#
 #35
-15#
-1:#
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-17#
-1y"
-1=#
-1!#
-09#
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-b1111 :
-b1111 3"
-b1111 -
-b1111 +
-b1111 8
-b1111 .
-b1111 >
 1{
 1'"
 b1111 ?
@ -1889,39 +1715,10 @@ b1111 g
 b1111 >#
 b1111 G#
 #40
-15#
-08#
-1:#
-11#
-09#
-0{"
-1y"
-17#
-1=#
-06#
-1!#
-1;#
-12#
-0`"
-1t"
-1<#
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-b1100 6"
-1v"
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-1["
 1`$
 0X$
 1C
-13#
-1u"
-1Z"
 1\$
-b10101 "
-b10101 6
-b10101 ;"
 1."
 14$
 1P$
@ -1930,8 +1727,6 @@ b10101 ;"
 11$
 1|#
 1B$
-b1111 :
-b1111 3"
 1#"
 1<$
 1"$
@ -1948,7 +1743,6 @@ b1111 3"
 1M$
 1U$
 1]$
-b1111 -
 1""
 1!$
 1($
@ -1964,7 +1758,6 @@ b111 C$
 1I$
 0Q$
 1Y$
-b1111 +
 1y
 1h#
 1p#
@ -1980,7 +1773,6 @@ b1111 +
 1s#
 b1011 y#
 b1101 ?$
-b1111 8
 1!
 bz111 i
 1m
@ -2021,8 +1813,6 @@ b1100 A$
 0W$
 0^$
 1R
-b1111 .
-b1111 >
 1S
 1W
 1[
@ -2101,28 +1891,9 @@ b1111 h
 b1111 ?#
 b1111 H#
 #45
-05#
-b111 "
-b111 6
-b111 ;"
-14#
-0:#
-18#
-01#
-b1000 6"
-0y"
-0!#
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-1`"
-0t"
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-0c"
-b0 8"
-0["
-0Z"
 0M$
-b111 :
-b111 3"
 0\$
 b110 C$
 0F$
@ -2134,11 +1905,9 @@ b110 C$
 1G$
 1Q$
 0O$
-b111 -
 0|#
 0E$
 1L$
-b111 +
 1,$
 0.$
 04$
@ -2152,7 +1921,6 @@ b111 +
 03$
 1Y$
 0W$
-b111 8
 1K#
 0($
 10$
@ -2162,8 +1930,6 @@ b1101001 P#
 0X#
 b101 y#
 b110 ?$
-b111 .
-b111 >
 1n#
 0p#
 0u#
@ -2224,89 +1990,85 @@ b111 >#
 b111 G#
 #50
 0(#
-0)#
-0'#
+0<#
 00#
-0,#
+0'#
+06#
 0x"
+0,#
+1}"
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 0&#
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 1m"
 b0z 7"
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 0r"
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+0\"
 0]"
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+19#
 b0 "
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 b0 ;"
-0#
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+0L"
 0B"
 1D"
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 1`"
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-09$
-0a$
-0I#
+0=$
+0J#
 0H"
 0G"
 b0 :"
@ -2314,21 +2076,23 @@ b0 :"
 0c"
 b0 8"
 0["
+09$
+0a$
+0I#
+0="
+0>"
+0Z"
 0,"
 0!$
 00$
 02$
 0]$
-0="
-0>"
-0Z"
-b0 -
+b0 :
+b0 3"
 0#"
 0w#
 0K#
 0V$
-b0 :
-b0 3"
 0'"
 0%"
 0h#
@ -2337,7 +2101,7 @@ b0 3"
 01$
 0E$
 0L$
-b0 +
+b0 ,
 0""
 0c#
 0k#
@ -2347,7 +2111,6 @@ b0 y#
 0*$
 b0 ?$
 0U$
-b0 ,
 0w
 0W
 0_
@ -2375,7 +2138,6 @@ b0 C$
 b0 Q#
 b0 A$
 0Z$
-b0 8
 0{
 0y
 0D
@ -2397,10 +2159,7 @@ b0 8
 0O$
 0Y$
 0W$
-0f$
-b0 =
-b0 .
-b0 >
+1d$
 0v
 0d
 0f
@ -2422,9 +2181,9 @@ b0 H
 0D$
 0K$
 0S$
-0h$
+1g$
 1i$
-1d$
+0c$
 b100 3
 b100 j$
 bz000 i
--- a/project0.2/ALUTB.v
+++ b/project0.2/ALUTB.v
@ -19,17 +19,17 @@ ALU uut(
 initial begin
    $dumpfile("ALU.vcd"); // GTKWAVE SIMULTAIN DATA WAVEFORM
    $dumpvars; // ICARUS VERILOG ADD ALL VARIABLES
-    A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b000; #5;
-    A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b000; #5;
-    A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b000; #5;
-    A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b000; #5;
-    A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 3'b000; #5;
+    A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b011; #5;
+    A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b011; #5;
+    A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b011; #5;
+    A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b011; #5;
+    A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 3'b011; #5;

-    A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b001; #5;
-    A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b001; #5;
-    A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b001; #5;
-    A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
-    A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
+    A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b111; #5;
+    A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b111; #5;
+    A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b111; #5;
+    A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b111; #5;
+    A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b111; #5;

    A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b010; #5;
    A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b010; #5;
--- a/project0.2/arithmeticUnit.v
+++ b/project0.2/arithmeticUnit.v
@ -8,9 +8,9 @@ module arithmeticUnit (
 );

 wire [3:0] addY, subY;
-wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub;
+wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub, tempoverflow;

-addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(overflow));
+addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(tempoverflow));
 subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));

 and add1 (add_Y[0], opCode[0], addY[0]);
@ -28,4 +28,6 @@ and and10 (tempCSub, CarryOUTSUB, opCode[1]);
 and and11 (tempCAdd, CarryOUTADD, opCode[0]);
 or or4 (CarryOUT, tempCAdd, tempCSub);

+and add12 (overflow, opCode[0], tempoverflow);
+
 endmodule