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subtraction & multiplier

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k0rrluna
2024-12-20 21:28:15 +03:00
parent 8d4ec38521
commit 4363a50662
299 changed files with 6627 additions and 55786 deletions
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project0.2/ALUTB.v Normal file
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module ALUTB ();
reg [3:0] A, B;
reg CarryIN;
reg [2:0] opCodeA;
wire [3:0] Y;
wire CarryOUT, overflow;
ALU uut(
.A(A),
.B(B),
.CarryIN(CarryIN),
.opCodeA(opCodeA),
.Y(Y),
.CarryOUT(CarryOUT),
.overflow(overflow)
);
initial begin
$dumpfile("ALU.vcd"); // GTKWAVE SIMULTAIN DATA WAVEFORM
$dumpvars; // ICARUS VERILOG ADD ALL VARIABLES
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b000; #5;
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b000; #5;
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b000; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b000; #5;
A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 3'b000; #5;
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b001; #5;
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b001; #5;
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b001; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
$finish; //NOT CONTAIN CLK, BUT STILL STOPS CODE
end
endmodule