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verilog

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This commit is contained in:
k0rrluna
2024-07-07 15:51:02 +03:00
parent c1f0851a45
commit 339ae1f428
35 changed files with 26577 additions and 1 deletions
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gowin/seq_light_test/seq_light_test.gprj Normal file
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/seqBlink.v" type="file.verilog" enable="1"/>
<File path="src/seqBlinkTB.v" type="file.verilog" enable="0"/>
<File path="src/seq_light_test.cst" type="file.cst" enable="1"/>
</FileList>
</Project>