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verilog

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This commit is contained in:
k0rrluna
2024-07-07 15:51:02 +03:00
parent c1f0851a45
commit 339ae1f428
35 changed files with 26577 additions and 1 deletions
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10
gowin/seq_light_test/impl/temp/rtl_parser.result Normal file
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[
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v",
"InstLine" : 1,
"InstName" : "seqBlink",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v",
"ModuleLine" : 1,
"ModuleName" : "seqBlink"
}
]

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gowin/seq_light_test/impl/temp/rtl_parser_arg.json Normal file
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{
"Device" : "GW2A-18C",
"Files" : [
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v",
"Type" : "verilog"
}
],
"IncludePath" : [
],
"LoopLimit" : 2000,
"ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}

0
gowin/seq_light_test/impl/temp/style.css Normal file
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