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verilog

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This commit is contained in:
k0rrluna
2024-07-07 15:51:02 +03:00
parent c1f0851a45
commit 339ae1f428
35 changed files with 26577 additions and 1 deletions
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2
gowin/fpga_project/impl/fpga_project_process_config.json
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@ -18,7 +18,7 @@
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false,
"FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "",
"FREQUENCY_DIVIDER" : "1",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,