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verilog

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kaltinsoy committed 2024-07-07 15:51:02 +03:00
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commit 339ae1f428
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gowin/fpga_project/impl/fpga_project_process_config.json
+1 -1
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@@ -18,7 +18,7 @@
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false,
"FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "",
"FREQUENCY_DIVIDER" : "1",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,