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lab5

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This commit is contained in:
k0rrluna 2025-01-26 06:05:52 +03:00
parent 7605bbf473
commit 1b0958962c
9 changed files with 881 additions and 167 deletions
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209
iverilog/tobb/lab5/ayarliSayac
View File

@ -7,15 +7,15 @@
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55ffcf0ba4e0 .scope module, "ayarliSayacTB" "ayarliSayacTB" 2 1; S_0x55b4b9d0fd50 .scope module, "ayarliSayacTB" "ayarliSayacTB" 2 1;
.timescale 0 0; .timescale 0 0;
v0x55ffcf0d1530_0 .var "clk", 0 0; v0x55b4b9d66830_0 .var "clk", 0 0;
v0x55ffcf0d15f0_0 .var "en", 0 0; v0x55b4b9d668f0_0 .var "en", 0 0;
v0x55ffcf0d16c0_0 .var "rst", 0 0; v0x55b4b9d669c0_0 .var "rst", 0 0;
v0x55ffcf0d17c0_0 .net "sayac", 5 0, v0x55ffcf0d11f0_0; 1 drivers v0x55b4b9d66ac0_0 .net "sayac", 5 0, v0x55b4b9d664f0_0; 1 drivers
v0x55ffcf0d1890_0 .var "sayma_miktari", 2 0; v0x55b4b9d66b90_0 .var "sayma_miktari", 2 0;
v0x55ffcf0d1980_0 .var "sayma_yonu", 0 0; v0x55b4b9d66c80_0 .var "sayma_yonu", 0 0;
S_0x55ffcf0ba670 .scope module, "uut" "ayarliSayac" 2 8, 3 1 0, S_0x55ffcf0ba4e0; S_0x55b4b9d0fee0 .scope module, "uut" "sayac" 2 8, 3 1 0, S_0x55b4b9d0fd50;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "clk"; .port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rst"; .port_info 1 /INPUT 1 "rst";
@ -23,153 +23,166 @@ S_0x55ffcf0ba670 .scope module, "uut" "ayarliSayac" 2 8, 3 1 0, S_0x55ffcf0ba4e0
.port_info 3 /INPUT 3 "sayma_miktari"; .port_info 3 /INPUT 3 "sayma_miktari";
.port_info 4 /INPUT 1 "sayma_yonu"; .port_info 4 /INPUT 1 "sayma_yonu";
.port_info 5 /OUTPUT 6 "sayac"; .port_info 5 /OUTPUT 6 "sayac";
v0x55ffcf0a5c70_0 .net "clk", 0 0, v0x55ffcf0d1530_0; 1 drivers v0x55b4b9d4e5b0_0 .net "clk", 0 0, v0x55b4b9d66830_0; 1 drivers
v0x55ffcf0d0e80_0 .var "clk_divider", 1 0; v0x55b4b9d66180_0 .var "clk_divider", 1 0;
v0x55ffcf0d0f60_0 .net "en", 0 0, v0x55ffcf0d15f0_0; 1 drivers v0x55b4b9d66260_0 .net "en", 0 0, v0x55b4b9d668f0_0; 1 drivers
v0x55ffcf0d1000_0 .var "miktar", 2 0; v0x55b4b9d66300_0 .var "miktar", 2 0;
v0x55ffcf0d10e0_0 .net "rst", 0 0, v0x55ffcf0d16c0_0; 1 drivers v0x55b4b9d663e0_0 .net "rst", 0 0, v0x55b4b9d669c0_0; 1 drivers
v0x55ffcf0d11f0_0 .var "sayac", 5 0; v0x55b4b9d664f0_0 .var "sayac", 5 0;
v0x55ffcf0d12d0_0 .net "sayma_miktari", 2 0, v0x55ffcf0d1890_0; 1 drivers v0x55b4b9d665d0_0 .net "sayma_miktari", 2 0, v0x55b4b9d66b90_0; 1 drivers
v0x55ffcf0d13b0_0 .net "sayma_yonu", 0 0, v0x55ffcf0d1980_0; 1 drivers v0x55b4b9d666b0_0 .net "sayma_yonu", 0 0, v0x55b4b9d66c80_0; 1 drivers
E_0x55ffcf0b4e60/0 .event negedge, v0x55ffcf0a5c70_0; E_0x55b4b9d4f1d0/0 .event negedge, v0x55b4b9d4e5b0_0;
E_0x55ffcf0b4e60/1 .event posedge, v0x55ffcf0d10e0_0; E_0x55b4b9d4f1d0/1 .event posedge, v0x55b4b9d663e0_0;
E_0x55ffcf0b4e60 .event/or E_0x55ffcf0b4e60/0, E_0x55ffcf0b4e60/1; E_0x55b4b9d4f1d0 .event/or E_0x55b4b9d4f1d0/0, E_0x55b4b9d4f1d0/1;
.scope S_0x55ffcf0ba670; .scope S_0x55b4b9d0fee0;
T_0 ; T_0 ;
%pushi/vec4 0, 0, 6; %pushi/vec4 0, 0, 6;
%store/vec4 v0x55ffcf0d11f0_0, 0, 6; %store/vec4 v0x55b4b9d664f0_0, 0, 6;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55ffcf0d1000_0, 0, 3;
%pushi/vec4 0, 0, 2; %pushi/vec4 0, 0, 2;
%store/vec4 v0x55ffcf0d0e80_0, 0, 2; %store/vec4 v0x55b4b9d66180_0, 0, 2;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x55b4b9d66300_0, 0, 3;
%end; %end;
.thread T_0; .thread T_0;
.scope S_0x55ffcf0ba670; .scope S_0x55b4b9d0fee0;
T_1 ; T_1 ;
%wait E_0x55ffcf0b4e60; %wait E_0x55b4b9d4f1d0;
%load/vec4 v0x55ffcf0d10e0_0; %load/vec4 v0x55b4b9d663e0_0;
%flag_set/vec4 8; %flag_set/vec4 8;
%jmp/0xz T_1.0, 8; %jmp/0xz T_1.0, 8;
%pushi/vec4 0, 0, 6; %pushi/vec4 0, 0, 6;
%assign/vec4 v0x55ffcf0d11f0_0, 0; %assign/vec4 v0x55b4b9d664f0_0, 0;
%pushi/vec4 0, 0, 2; %pushi/vec4 0, 0, 2;
%assign/vec4 v0x55ffcf0d0e80_0, 0; %assign/vec4 v0x55b4b9d66180_0, 0;
%pushi/vec4 0, 0, 3;
%assign/vec4 v0x55b4b9d66300_0, 0;
%jmp T_1.1; %jmp T_1.1;
T_1.0 ; T_1.0 ;
%load/vec4 v0x55ffcf0d0e80_0; %load/vec4 v0x55b4b9d66180_0;
%addi 1, 0, 2; %addi 1, 0, 2;
%assign/vec4 v0x55ffcf0d0e80_0, 0; %assign/vec4 v0x55b4b9d66180_0, 0;
T_1.1 ; %load/vec4 v0x55b4b9d66180_0;
%load/vec4 v0x55ffcf0d0e80_0;
%cmpi/e 3, 0, 2; %cmpi/e 3, 0, 2;
%jmp/0xz T_1.2, 4; %jmp/0xz T_1.2, 4;
%load/vec4 v0x55ffcf0d0f60_0; %pushi/vec4 0, 0, 2;
%assign/vec4 v0x55b4b9d66180_0, 0;
%load/vec4 v0x55b4b9d66260_0;
%flag_set/vec4 8; %flag_set/vec4 8;
%jmp/0xz T_1.4, 8; %jmp/0xz T_1.4, 8;
%load/vec4 v0x55ffcf0d12d0_0; %load/vec4 v0x55b4b9d665d0_0;
%assign/vec4 v0x55ffcf0d1000_0, 0; %assign/vec4 v0x55b4b9d66300_0, 0;
%load/vec4 v0x55ffcf0d13b0_0; T_1.4 ;
%pad/u 32; %load/vec4 v0x55b4b9d666b0_0;
%cmpi/e 1, 0, 32; %flag_set/vec4 8;
%jmp/0xz T_1.6, 4; %jmp/0xz T_1.6, 8;
%load/vec4 v0x55ffcf0d11f0_0; %load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55ffcf0d1000_0; %load/vec4 v0x55b4b9d66300_0;
%pad/u 6; %pad/u 6;
%add; %add;
%cmpi/u 63, 0, 6; %cmpi/u 63, 0, 6;
%flag_inv 5; GE is !LT %flag_inv 5; GE is !LT
%jmp/0xz T_1.8, 5; %jmp/0xz T_1.8, 5;
%pushi/vec4 63, 0, 6; %pushi/vec4 63, 0, 6;
%assign/vec4 v0x55ffcf0d11f0_0, 0; %assign/vec4 v0x55b4b9d664f0_0, 0;
%jmp T_1.9; %jmp T_1.9;
T_1.8 ; T_1.8 ;
%load/vec4 v0x55ffcf0d1000_0; %load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55b4b9d66300_0;
%pad/u 6; %pad/u 6;
%load/vec4 v0x55ffcf0d11f0_0;
%add; %add;
%assign/vec4 v0x55ffcf0d11f0_0, 0; %assign/vec4 v0x55b4b9d664f0_0, 0;
T_1.9 ; T_1.9 ;
%jmp T_1.7; %jmp T_1.7;
T_1.6 ; T_1.6 ;
%load/vec4 v0x55ffcf0d11f0_0; %load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55ffcf0d1000_0; %load/vec4 v0x55b4b9d66300_0;
%pad/u 6; %pad/u 6;
%sub; %cmp/u;
%cmpi/u 0, 0, 6;
%flag_or 5, 4; %flag_or 5, 4;
%jmp/0xz T_1.10, 5; %jmp/0xz T_1.10, 5;
%pushi/vec4 0, 0, 6; %pushi/vec4 0, 0, 6;
%assign/vec4 v0x55ffcf0d11f0_0, 0; %assign/vec4 v0x55b4b9d664f0_0, 0;
%jmp T_1.11; %jmp T_1.11;
T_1.10 ; T_1.10 ;
%load/vec4 v0x55ffcf0d11f0_0; %load/vec4 v0x55b4b9d664f0_0;
%load/vec4 v0x55ffcf0d1000_0; %load/vec4 v0x55b4b9d66300_0;
%pad/u 6; %pad/u 6;
%sub; %sub;
%assign/vec4 v0x55ffcf0d11f0_0, 0; %assign/vec4 v0x55b4b9d664f0_0, 0;
T_1.11 ; T_1.11 ;
T_1.7 ; T_1.7 ;
T_1.4 ;
T_1.2 ; T_1.2 ;
T_1.1 ;
%jmp T_1; %jmp T_1;
.thread T_1; .thread T_1;
.scope S_0x55ffcf0ba4e0; .scope S_0x55b4b9d0fd50;
T_2 ; T_2 ;
%load/vec4 v0x55ffcf0d1530_0; %load/vec4 v0x55b4b9d66830_0;
%inv; %inv;
%store/vec4 v0x55ffcf0d1530_0, 0, 1; %store/vec4 v0x55b4b9d66830_0, 0, 1;
%delay 1, 0; %delay 1, 0;
%jmp T_2; %jmp T_2;
.thread T_2; .thread T_2;
.scope S_0x55ffcf0ba4e0; .scope S_0x55b4b9d0fd50;
T_3 ; T_3 ;
%vpi_call 2 22 "$dumpfile", "ayarliSayac.vcd" {0 0 0}; %vpi_call 2 22 "$dumpfile", "ayarliSayac.vcd" {0 0 0};
%vpi_call 2 23 "$dumpvars" {0 0 0}; %vpi_call 2 23 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55ffcf0d1530_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55ffcf0d16c0_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d15f0_0, 0, 1; %store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 6, 0, 3; %pushi/vec4 0, 0, 1;
%store/vec4 v0x55ffcf0d1890_0, 0, 3; %store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d1980_0, 0, 1; %store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 32, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 8, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 64, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 16, 0; %delay 16, 0;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d1530_0, 0, 1; %store/vec4 v0x55b4b9d66830_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d16c0_0, 0, 1; %store/vec4 v0x55b4b9d669c0_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d15f0_0, 0, 1; %store/vec4 v0x55b4b9d668f0_0, 0, 1;
%pushi/vec4 2, 0, 3; %pushi/vec4 2, 0, 3;
%store/vec4 v0x55ffcf0d1890_0, 0, 3; %store/vec4 v0x55b4b9d66b90_0, 0, 3;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d1980_0, 0, 1; %store/vec4 v0x55b4b9d66c80_0, 0, 1;
%delay 8, 0; %delay 8, 0;
%pushi/vec4 1, 0, 1; %vpi_call 2 29 "$finish" {0 0 0};
%store/vec4 v0x55ffcf0d1530_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55ffcf0d16c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d15f0_0, 0, 1;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55ffcf0d1890_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d1980_0, 0, 1;
%delay 8, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d1530_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d16c0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d15f0_0, 0, 1;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55ffcf0d1890_0, 0, 3;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55ffcf0d1980_0, 0, 1;
%delay 8, 0;
%vpi_call 2 28 "$finish" {0 0 0};
%end; %end;
.thread T_3; .thread T_3;
# The file index is used to find the file name in the following table. # The file index is used to find the file name in the following table.
@ -177,4 +190,4 @@ T_3 ;
"N/A"; "N/A";
"<interactive>"; "<interactive>";
"ayarliSayacTB.v"; "ayarliSayacTB.v";
"ayarliSayac.v"; "sayac.v";

2
iverilog/tobb/lab5/ayarliSayac.v
View File

@ -23,7 +23,7 @@ module ayarliSayac (
end end
if (clk_divider == 2'b11) begin if (clk_divider == 2'b11) begin
if (en) begin if (en) begin
miktar <= sayma_miktari; miktar = sayma_miktari;
if (sayma_yonu == 1) begin if (sayma_yonu == 1) begin
if (sayac + miktar >= 6'b1111_11) begin if (sayac + miktar >= 6'b1111_11) begin
sayac <= 6'b1111_11; sayac <= 6'b1111_11;

365
iverilog/tobb/lab5/ayarliSayac.vcd
View File

@ -1,5 +1,5 @@
$date $date
Sat Jan 25 07:58:46 2025 Sun Jan 26 04:55:11 2025
$end $end
$version $version
Icarus Verilog Icarus Verilog
@ -29,127 +29,364 @@ $enddefinitions $end
#0 #0
$dumpvars $dumpvars
b0 * b0 *
b1 ) b0 )
b1 ( b0 (
b110 ' b111 '
1& 1&
b110 % b111 %
0$ 0$
1# 1#
0" 1"
b0 ! b0 !
$end $end
#1 #1
1"
#2
b10 (
0"
#3
1"
#4
b11 (
0"
#5
1"
#6
b1 !
b1 *
b110 )
b0 (
0"
#7
1"
#8
b1 ( b1 (
0" 0"
#9 #2
1" 1"
#10 #3
b10 ( b10 (
0" 0"
#11 #4
1" 1"
#12 #5
b11 ( b11 (
0" 0"
#13 #6
1" 1"
#7
b111 )
b0 (
0"
#8
1"
#9
b1 (
0"
#10
1"
#11
b10 (
0"
#12
1"
#13
b11 (
0"
#14 #14
1"
#15
b111 ! b111 !
b111 * b111 *
b0 ( b0 (
0" 0"
#15
1"
#16 #16
1"
#17
b1 ( b1 (
0" 0"
b10 %
b10 '
0#
#17
1"
#18 #18
1"
#19
b10 ( b10 (
0" 0"
#19
1"
#20 #20
1"
#21
b11 ( b11 (
0" 0"
#21
1"
#22 #22
1"
#23
b1110 !
b1110 *
b0 ( b0 (
0" 0"
#23
1"
#24 #24
1"
#25
b1 ( b1 (
0" 0"
b11 %
b11 '
1#
#25
1"
#26 #26
1"
#27
b10 ( b10 (
0" 0"
#27
1"
#28 #28
1"
#29
b11 ( b11 (
0" 0"
#29
1"
#30 #30
1"
#31
b10101 !
b10101 *
b0 (
0"
#32
b1 (
0"
#33
1"
#34
b10 (
0"
#35
1"
#36
b11 (
0"
#37
1"
#38
b11100 !
b11100 *
b0 (
0"
#39
1"
#40
b1 (
0"
#41
1"
#42
b10 (
0"
#43
1"
#44
b11 (
0"
#45
1"
#46
b100011 !
b100011 *
b0 (
0"
#47
1"
#48
b1 (
0"
#49
1"
#50
b10 (
0"
#51
1"
#52
b11 (
0"
#53
1"
#54
b101010 !
b101010 *
b0 (
0"
#55
1"
#56
b1 (
0"
#57
1"
#58
b10 (
0"
#59
1"
#60
b11 (
0"
#61
1"
#62
b110001 !
b110001 *
b0 (
0"
#63
1"
#64
b1 (
0"
#65
1"
#66
b10 (
0"
#67
1"
#68
b11 (
0"
#69
1"
#70
b111000 !
b111000 *
b0 (
0"
#71
1"
#72
b1 (
0"
#73
1"
#74
b10 (
0"
#75
1"
#76
b11 (
0"
#77
1"
#78
b111111 !
b111111 *
b0 (
0"
#79
1"
#80
b1 (
0"
#81
1"
#82
b10 (
0"
#83
1"
#84
b11 (
0"
#85
1"
#86
b110 !
b110 *
b0 (
0"
#87
1"
#88
b1 (
0"
#89
1"
#90
b10 (
0"
#91
1"
#92
b11 (
0"
#93
1"
#94
b1101 ! b1101 !
b1101 * b1101 *
b11 )
b0 ( b0 (
0" 0"
#31 #95
1" 1"
#32 #96
b1 (
0"
#97
1"
#98
b10 (
0"
#99
1"
#100
b11 (
0"
#101
1"
#102
b10100 !
b10100 *
b0 (
0"
#103
1"
#104
b1 (
0"
#105
1"
#106
b10 (
0"
#107
1"
#108
b11 (
0"
#109
1"
#110
b11011 !
b11011 *
b0 (
0"
#111
1"
#112
b1 (
0"
#113
1"
#114
b10 (
0"
#115
1"
#116
b11 (
0"
#117
1"
#118
b100010 !
b100010 *
b0 (
0"
#119
1"
#120
b0 )
b0 ! b0 !
b0 * b0 *
0" 0"
b10 % b10 %
b10 ' b10 '
1$ 1$
#33 #121
1" 1"
#34 #122
0" 0"
#35 #123
1" 1"
#36 #124
0" 0"
#37 #125
1" 1"
#38 #126
0" 0"
#39 #127
1" 1"
#40 #128
0" 0"

9
iverilog/tobb/lab5/ayarliSayacTB.v
View File

@ -5,7 +5,7 @@ module ayarliSayacTB();
reg sayma_yonu; reg sayma_yonu;
wire [5:0] sayac; wire [5:0] sayac;
ayarliSayac uut ( sayac uut (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
.en(en), .en(en),
@ -21,9 +21,10 @@ end
initial begin initial begin
$dumpfile("ayarliSayac.vcd"); $dumpfile("ayarliSayac.vcd");
$dumpvars; $dumpvars;
clk = 0; rst = 0; en = 1; sayma_miktari = 3'b110; sayma_yonu = 1'b1; #16; clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #32;
clk = 1; rst = 0; en = 0; sayma_miktari = 3'b010; sayma_yonu = 1'b1; #8; clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #8;
clk = 1; rst = 0; en = 1; sayma_miktari = 3'b011; sayma_yonu = 1'b1; #8; clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #64;
clk = 1; rst = 0; en = 1; sayma_miktari = 3'b111; sayma_yonu = 1'b1; #16;
clk = 1; rst = 1; en = 1; sayma_miktari = 3'b010; sayma_yonu = 1'b1; #8; clk = 1; rst = 1; en = 1; sayma_miktari = 3'b010; sayma_yonu = 1'b1; #8;
$finish; $finish;
end end

48
iverilog/tobb/lab5/sayac.v Normal file
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@ -0,0 +1,48 @@
module sayac (
input clk, rst, en,
input [2:0] sayma_miktari,
input sayma_yonu,
output reg [5:0] sayac
);
reg [1:0] clk_divider;
reg [2:0] miktar;
initial begin
sayac = 6'b0000_00;
miktar = 3'b001;
clk_divider = 2'b00;
end
always@(*) begin
miktar = sayma_miktari;
end
always@(negedge clk or posedge rst) begin
if (rst) begin
sayac <= 6'b0000_00;
clk_divider <= 2'b00;
end else begin
clk_divider <= clk_divider + 1;
end
if (clk_divider == 2'b11) begin
clk_divider <= 2'b00;
if (en) begin
if (sayma_miktari) begin
if (sayac + miktar >= 6'b1111_11) begin
sayac <= 6'b1111_11;
end else begin
sayac <= sayac + miktar;
end
end else begin
if (miktar >= sayac) begin
sayac <= 6'b0000_00;
end else begin
sayac <= sayac - miktar;
end
end
end
end
end
endmodule

177
iverilog/tobb/lab5/tetris Normal file
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@ -0,0 +1,177 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x56335d23e170 .scope module, "tetrisTB" "tetrisTB" 2 1;
.timescale 0 0;
v0x56335d253500_0 .net "bitti_mi", 0 0, v0x56335d200370_0; 1 drivers
v0x56335d2535c0_0 .net "cevrim", 3 0, v0x56335d200c00_0; 1 drivers
v0x56335d253690_0 .var "clk", 0 0;
v0x56335d253790_0 .var "p", 2 0;
v0x56335d253860_0 .net "yukseklik", 3 0, v0x56335d253090_0; 1 drivers
S_0x56335d23e300 .scope module, "uut" "tetris" 2 9, 3 1 0, S_0x56335d23e170;
.timescale 0 0;
.port_info 0 /INPUT 3 "parca";
.port_info 1 /INPUT 1 "clk";
.port_info 2 /OUTPUT 4 "yukseklik";
.port_info 3 /OUTPUT 1 "bitti_mi";
.port_info 4 /OUTPUT 4 "cevrim";
v0x56335d200370_0 .var "bitti_mi", 0 0;
v0x56335d200c00_0 .var "cevrim", 3 0;
v0x56335d252ee0_0 .net "clk", 0 0, v0x56335d253690_0; 1 drivers
v0x56335d252fb0_0 .net "parca", 2 0, v0x56335d253790_0; 1 drivers
v0x56335d253090_0 .var "yukseklik", 3 0;
v0x56335d2531c0_0 .var "yukseklik1", 3 0;
v0x56335d2532a0_0 .var "yukseklik2", 3 0;
v0x56335d253380_0 .var "yukseklik3", 3 0;
E_0x56335d238670 .event posedge, v0x56335d252ee0_0;
.scope S_0x56335d23e300;
T_0 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d200c00_0, 0, 4;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56335d200370_0, 0, 1;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d253090_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d2531c0_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d2532a0_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x56335d253380_0, 0, 4;
%end;
.thread T_0;
.scope S_0x56335d23e300;
T_1 ;
%wait E_0x56335d238670;
%load/vec4 v0x56335d200370_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_1.0, 8;
%load/vec4 v0x56335d252fb0_0;
%parti/s 1, 0, 2;
%flag_set/vec4 8;
%jmp/0xz T_1.2, 8;
%load/vec4 v0x56335d2531c0_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d2531c0_0, 0;
T_1.2 ;
%load/vec4 v0x56335d252fb0_0;
%parti/s 1, 1, 2;
%flag_set/vec4 8;
%jmp/0xz T_1.4, 8;
%load/vec4 v0x56335d2532a0_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d2532a0_0, 0;
T_1.4 ;
%load/vec4 v0x56335d252fb0_0;
%parti/s 1, 2, 3;
%flag_set/vec4 8;
%jmp/0xz T_1.6, 8;
%load/vec4 v0x56335d253380_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d253380_0, 0;
T_1.6 ;
%load/vec4 v0x56335d200c00_0;
%addi 1, 0, 4;
%assign/vec4 v0x56335d200c00_0, 0;
%load/vec4 v0x56335d200c00_0;
%cmpi/e 15, 0, 4;
%jmp/0xz T_1.8, 4;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x56335d200370_0, 0;
T_1.8 ;
T_1.0 ;
%jmp T_1;
.thread T_1;
.scope S_0x56335d23e300;
T_2 ;
%wait E_0x56335d238670;
%load/vec4 v0x56335d200370_0;
%flag_set/vec4 8;
%jmp/0xz T_2.0, 8;
%load/vec4 v0x56335d2532a0_0;
%load/vec4 v0x56335d2531c0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%load/vec4 v0x56335d253380_0;
%load/vec4 v0x56335d2531c0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_2.2, 8;
%load/vec4 v0x56335d2531c0_0;
%assign/vec4 v0x56335d253090_0, 0;
%jmp T_2.3;
T_2.2 ;
%load/vec4 v0x56335d2531c0_0;
%load/vec4 v0x56335d2532a0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%load/vec4 v0x56335d253380_0;
%load/vec4 v0x56335d2532a0_0;
%cmp/u;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%and;
%flag_set/vec4 8;
%jmp/0xz T_2.4, 8;
%load/vec4 v0x56335d2532a0_0;
%assign/vec4 v0x56335d253090_0, 0;
%jmp T_2.5;
T_2.4 ;
%load/vec4 v0x56335d253380_0;
%assign/vec4 v0x56335d253090_0, 0;
T_2.5 ;
T_2.3 ;
T_2.0 ;
%jmp T_2;
.thread T_2;
.scope S_0x56335d23e170;
T_3 ;
%load/vec4 v0x56335d253690_0;
%inv;
%store/vec4 v0x56335d253690_0, 0, 1;
%delay 1, 0;
%jmp T_3;
.thread T_3;
.scope S_0x56335d23e170;
T_4 ;
%vpi_call 2 22 "$dumpfile", "tetris.vcd" {0 0 0};
%vpi_call 2 23 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56335d253690_0, 0, 1;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 2, 0;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 2, 0;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 2, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x56335d253790_0, 0, 3;
%delay 30, 0;
%vpi_call 2 28 "$finish" {0 0 0};
%end;
.thread T_4;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tetrisTB.v";
"tetris.v";

49
iverilog/tobb/lab5/tetris.v Normal file
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@ -0,0 +1,49 @@
module tetris (
input [2:0] parca,
input clk,
output reg [3:0] yukseklik,
output reg bitti_mi,
output reg [3:0] cevrim
);
reg [3:0] yukseklik1, yukseklik2, yukseklik3;
initial begin
cevrim = 4'd0;
bitti_mi = 1'b0;
yukseklik = 4'b0;
yukseklik1 = 4'd0;
yukseklik2 = 4'd0;
yukseklik3 = 4'd0;
end
always@(posedge clk) begin
if (!bitti_mi) begin
if (parca[0]) begin
yukseklik1 <= yukseklik1 + 1;
end if (parca[1]) begin
yukseklik2 <= yukseklik2 + 1;
end if (parca[2]) begin
yukseklik3 <= yukseklik3 + 1;
end
cevrim <= cevrim + 1;
if (cevrim == 4'd15) begin
bitti_mi <= 1'b1;
end
end
end
always@(posedge clk) begin //comperator
if (bitti_mi) begin
if (yukseklik1 >= yukseklik2 && yukseklik1 >= yukseklik3) begin
yukseklik <= yukseklik1;
end else if (yukseklik2 >= yukseklik1 && yukseklik2 >= yukseklik3) begin
yukseklik <= yukseklik2;
end else begin
yukseklik <= yukseklik3;
end
end
end
endmodule

158
iverilog/tobb/lab5/tetris.vcd Normal file
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@ -0,0 +1,158 @@
$date
Sun Jan 26 06:03:11 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tetrisTB $end
$var wire 4 ! yukseklik [3:0] $end
$var wire 4 " cevrim [3:0] $end
$var wire 1 # bitti_mi $end
$var reg 1 $ clk $end
$var reg 3 % p [2:0] $end
$scope module uut $end
$var wire 1 $ clk $end
$var wire 3 & parca [2:0] $end
$var reg 1 # bitti_mi $end
$var reg 4 ' cevrim [3:0] $end
$var reg 4 ( yukseklik [3:0] $end
$var reg 4 ) yukseklik1 [3:0] $end
$var reg 4 * yukseklik2 [3:0] $end
$var reg 4 + yukseklik3 [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 +
b0 *
b0 )
b0 (
b0 '
b10 &
b10 %
0$
0#
b0 "
b0 !
$end
#1
b1 "
b1 '
b1 *
1$
#2
0$
b11 %
b11 &
#3
b10 "
b10 '
b10 *
b1 )
1$
#4
0$
b10 %
b10 &
#5
b11 "
b11 '
b11 *
1$
#6
0$
b0 %
b0 &
#7
b100 "
b100 '
1$
#8
0$
#9
b101 "
b101 '
1$
#10
0$
#11
b110 "
b110 '
1$
#12
0$
#13
b111 "
b111 '
1$
#14
0$
#15
b1000 "
b1000 '
1$
#16
0$
#17
b1001 "
b1001 '
1$
#18
0$
#19
b1010 "
b1010 '
1$
#20
0$
#21
b1011 "
b1011 '
1$
#22
0$
#23
b1100 "
b1100 '
1$
#24
0$
#25
b1101 "
b1101 '
1$
#26
0$
#27
b1110 "
b1110 '
1$
#28
0$
#29
b1111 "
b1111 '
1$
#30
0$
#31
1#
b0 "
b0 '
1$
#32
0$
#33
b11 !
b11 (
1$
#34
0$
#35
1$
#36
0$

31
iverilog/tobb/lab5/tetrisTB.v Normal file
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@ -0,0 +1,31 @@
module tetrisTB();
reg [2:0] p;
reg clk;
wire [3:0] yukseklik;
wire bitti_mi;
wire [3:0] cevrim;
tetris uut (
.parca(p),
.clk(clk),
.yukseklik(yukseklik),
.bitti_mi(bitti_mi),
.cevrim(cevrim)
);
always begin
clk = ~clk; #1;
end
initial begin
$dumpfile("tetris.vcd");
$dumpvars;
clk = 0; p = 3'b010; #2;
p = 3'b011; #2;
p = 3'b010; #2;
p = 3'b000; #30;
$finish;
end
endmodule