lab5

iverilog/tobb/lab5/tetris.vcd

@@ -0,0 +1,158 @@
+$date
+	Sun Jan 26 06:03:11 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module tetrisTB $end
+$var wire 4 ! yukseklik [3:0] $end
+$var wire 4 " cevrim [3:0] $end
+$var wire 1 # bitti_mi $end
+$var reg 1 $ clk $end
+$var reg 3 % p [2:0] $end
+$scope module uut $end
+$var wire 1 $ clk $end
+$var wire 3 & parca [2:0] $end
+$var reg 1 # bitti_mi $end
+$var reg 4 ' cevrim [3:0] $end
+$var reg 4 ( yukseklik [3:0] $end
+$var reg 4 ) yukseklik1 [3:0] $end
+$var reg 4 * yukseklik2 [3:0] $end
+$var reg 4 + yukseklik3 [3:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b0 +
+b0 *
+b0 )
+b0 (
+b0 '
+b10 &
+b10 %
+0$
+0#
+b0 "
+b0 !
+$end
+#1
+b1 "
+b1 '
+b1 *
+1$
+#2
+0$
+b11 %
+b11 &
+#3
+b10 "
+b10 '
+b10 *
+b1 )
+1$
+#4
+0$
+b10 %
+b10 &
+#5
+b11 "
+b11 '
+b11 *
+1$
+#6
+0$
+b0 %
+b0 &
+#7
+b100 "
+b100 '
+1$
+#8
+0$
+#9
+b101 "
+b101 '
+1$
+#10
+0$
+#11
+b110 "
+b110 '
+1$
+#12
+0$
+#13
+b111 "
+b111 '
+1$
+#14
+0$
+#15
+b1000 "
+b1000 '
+1$
+#16
+0$
+#17
+b1001 "
+b1001 '
+1$
+#18
+0$
+#19
+b1010 "
+b1010 '
+1$
+#20
+0$
+#21
+b1011 "
+b1011 '
+1$
+#22
+0$
+#23
+b1100 "
+b1100 '
+1$
+#24
+0$
+#25
+b1101 "
+b1101 '
+1$
+#26
+0$
+#27
+b1110 "
+b1110 '
+1$
+#28
+0$
+#29
+b1111 "
+b1111 '
+1$
+#30
+0$
+#31
+1#
+b0 "
+b0 '
+1$
+#32
+0$
+#33
+b11 !
+b11 (
+1$
+#34
+0$
+#35
+1$
+#36
+0$