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rearrangement

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k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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52
tests/test2v.vcd
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@ -1,26 +1,26 @@
$date
Tue Jul 9 19:50:51 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module test2Tb $end
$var wire 7 ! b [6:0] $end
$var reg 4 " a [3:0] $end
$scope module uut $end
$var wire 4 # a [3:0] $end
$var wire 7 $ b [6:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b111110 $
b101 #
b101 "
b111110 !
$end
#10
$date
Tue Jul 9 19:50:51 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module test2Tb $end
$var wire 7 ! b [6:0] $end
$var reg 4 " a [3:0] $end
$scope module uut $end
$var wire 4 # a [3:0] $end
$var wire 7 $ b [6:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b111110 $
b101 #
b101 "
b111110 !
$end
#10