rearrangement
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@ -1,8 +1,8 @@
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module test2 (
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input [3:0] a,
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output [6:0] b
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);
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assign b = (1 << (a + 1)) - 2;
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module test2 (
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input [3:0] a,
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output [6:0] b
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);
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assign b = (1 << (a + 1)) - 2;
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endmodule
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