kaltinsoy/verilog
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rearrangement

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This commit is contained in:
k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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34
tests/hello_tb.v
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@ -1,17 +1,17 @@
module hello_tb();
reg A;
reg B;
wire C, D;
initial begin
$dumpfile("dmp.vcd");
$dumpvars;
A = 0; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1; #10;
$finish;
end
endmodule
module hello_tb();
reg A;
reg B;
wire C, D;
initial begin
$dumpfile("dmp.vcd");
$dumpvars;
A = 0; B = 0; #10;
A = 0; B = 1; #10;
A = 1; B = 0; #10;
A = 1; B = 1; #10;
$finish;
end
endmodule