rearrangement
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@ -1,9 +1,9 @@
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module hello(
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input wire A, B,
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output wire C, D
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);
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and(D, A, B);
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xor(C, A, B);
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endmodule
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module hello(
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input wire A, B,
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output wire C, D
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);
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and(D, A, B);
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xor(C, A, B);
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endmodule
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