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rearrangement

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k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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80
tests/dmp.vcd
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@ -1,40 +1,40 @@
$date
Sat Apr 06 17:40:37 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module hello $end
$var wire 1 ! A $end
$var wire 1 " B $end
$var wire 1 # C $end
$var wire 1 $ D $end
$upscope $end
$scope module hello_tb $end
$var reg 1 % A $end
$var reg 1 & B $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
0&
0%
x$
x#
z"
z!
$end
#10
1&
#20
0&
1%
#30
1&
#40
$date
Sat Apr 06 17:40:37 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module hello $end
$var wire 1 ! A $end
$var wire 1 " B $end
$var wire 1 # C $end
$var wire 1 $ D $end
$upscope $end
$scope module hello_tb $end
$var reg 1 % A $end
$var reg 1 & B $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
0&
0%
x$
x#
z"
z!
$end
#10
1&
#20
0&
1%
#30
1&
#40