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rearrangement

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This commit is contained in:
k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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22
iverilog/tobb/labs/lab4/lab4.v Normal file
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module lab4(
input [8:0] signal,
output reg [3:0] S
);
always@(*) begin
S = 4'b0000;
if (signal[8] == 1) begin //First most significant bit -> sum
S = signal[5:3] + signal[2:0];
end
else if (signal[7] == 1) begin
S = signal[5:3] - signal [2:0];
end
else if (signal[6] == 1) begin
S = signal[5:3] & signal [2:0];
end
else if (signal[6] == 0) begin
S = signal[5:3] | signal [2:0];
end
end
endmodule

114
iverilog/tobb/labs/lab4/lab4o Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55d6490fdb70 .scope module, "lab4tb" "lab4tb" 2 1;
.timescale 0 0;
v0x55d64910fee0_0 .var "s1", 8 0;
v0x55d64910ffa0_0 .net "s2", 3 0, v0x55d6490c37f0_0; 1 drivers
S_0x55d6490fdd00 .scope module, "uut" "lab4" 2 6, 3 1 0, S_0x55d6490fdb70;
.timescale 0 0;
.port_info 0 /INPUT 9 "signal";
.port_info 1 /OUTPUT 4 "S";
v0x55d6490c37f0_0 .var "S", 3 0;
v0x55d6490c3c00_0 .net "signal", 8 0, v0x55d64910fee0_0; 1 drivers
E_0x55d6490c2340 .event edge, v0x55d6490c3c00_0;
.scope S_0x55d6490fdd00;
T_0 ;
%wait E_0x55d6490c2340;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55d6490c37f0_0, 0, 4;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 1, 8, 5;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.0, 4;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 3, 0, 2;
%pad/u 4;
%add;
%store/vec4 v0x55d6490c37f0_0, 0, 4;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 1, 7, 4;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.2, 4;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 3, 0, 2;
%pad/u 4;
%sub;
%store/vec4 v0x55d6490c37f0_0, 0, 4;
%jmp T_0.3;
T_0.2 ;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 1, 6, 4;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.4, 4;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 3, 0, 2;
%pad/u 4;
%and;
%store/vec4 v0x55d6490c37f0_0, 0, 4;
%jmp T_0.5;
T_0.4 ;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 1, 6, 4;
%pad/u 32;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.6, 4;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x55d6490c3c00_0;
%parti/s 3, 0, 2;
%pad/u 4;
%or;
%store/vec4 v0x55d6490c37f0_0, 0, 4;
T_0.6 ;
T_0.5 ;
T_0.3 ;
T_0.1 ;
%jmp T_0;
.thread T_0, $push;
.scope S_0x55d6490fdb70;
T_1 ;
%vpi_call 2 12 "$dumpfile", "lab4v.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 297, 0, 9;
%store/vec4 v0x55d64910fee0_0, 0, 9;
%delay 10, 0;
%pushi/vec4 169, 0, 9;
%store/vec4 v0x55d64910fee0_0, 0, 9;
%delay 10, 0;
%pushi/vec4 105, 0, 9;
%store/vec4 v0x55d64910fee0_0, 0, 9;
%delay 10, 0;
%pushi/vec4 41, 0, 9;
%store/vec4 v0x55d64910fee0_0, 0, 9;
%delay 10, 0;
%vpi_call 2 19 "$display", "Done" {0 0 0};
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"lab4tb.v";
"lab4.v";

22
iverilog/tobb/labs/lab4/lab4tb.v Normal file
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module lab4tb();
reg [8:0] s1;
wire [3:0] s2;
lab4 uut(
.signal(s1),
.S(s2)
);
initial begin
$dumpfile("lab4v.vcd");
$dumpvars;
s1 = 9'b100_101_001; #10;
s1 = 9'b010_101_001; #10;
s1 = 9'b001_101_001; #10;
s1 = 9'b000_101_001; #10;
$display("Done");
end
endmodule

41
iverilog/tobb/labs/lab4/lab4v.vcd Normal file
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$date
Fri Jul 5 05:10:51 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module lab4tb $end
$var wire 4 ! s2 [3:0] $end
$var reg 9 " s1 [8:0] $end
$scope module uut $end
$var wire 9 # signal [8:0] $end
$var reg 4 $ S [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b110 $
b100101001 #
b100101001 "
b110 !
$end
#10
b100 !
b100 $
b10101001 "
b10101001 #
#20
b1 !
b1 $
b1101001 "
b1101001 #
#30
b101 !
b101 $
b101001 "
b101001 #
#40