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rearrangement

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This commit is contained in:
k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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54
iverilog/tobb/labs/lab3/impl/temp/rtl_parser.result Normal file
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[
{
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"InstLine" : 1,
"InstName" : "fullAdder",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"ModuleLine" : 1,
"ModuleName" : "fullAdder",
"SubInsts" : [
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
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"InstName" : "h0",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
"ModuleLine" : 1,
"ModuleName" : "halfAdder"
},
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
"ModuleLine" : 1,
"ModuleName" : "halfAdder"
}
]
},
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
"InstLine" : 1,
"InstName" : "mult2bit",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
"ModuleLine" : 1,
"ModuleName" : "mult2bit",
"SubInsts" : [
{
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"InstName" : "h0",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
"ModuleLine" : 1,
"ModuleName" : "halfAdder"
},
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
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"InstName" : "h1",
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"ModuleLine" : 1,
"ModuleName" : "halfAdder"
}
]
}
]

25
iverilog/tobb/labs/lab3/impl/temp/rtl_parser_arg.json Normal file
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{
"Device" : "GW2A-18C",
"Files" : [
{
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"Type" : "verilog"
},
{
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
"Type" : "verilog"
},
{
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
"Type" : "verilog"
}
],
"IncludePath" : [
],
"LoopLimit" : 2000,
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab3/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}

0
iverilog/tobb/labs/lab3/impl/temp/style.css Normal file
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