kaltinsoy/verilog
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rearrangement

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This commit is contained in:
k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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5
iverilog/tobb/labs/lab3/impl/gwsynthesis/lab3_syn_rsc.xml Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<Module name="mult2bit" Lut="1" T_Lut="4(1)">
<SubModule name="h0" Lut="1" T_Lut="1(1)"/>
<SubModule name="h1" Lut="2" T_Lut="2(2)"/>
</Module>