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rearrangement

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k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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iverilog/tobb/labs/lab3/impl/gwsynthesis/lab3.prj Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v" type="verilog"/>
<File path="C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v" type="verilog"/>
<File path="C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>