rearrangement

iverilog/tobb/labs/lab2_prep/impl/gwsynthesis/lab2.log

@@ -0,0 +1,40 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\lab2.v'
+Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\tb.v'
+Compiling module 'tb'("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
+WARN  (EX3858) : System task 'dumpfile' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":17)
+WARN  (EX3858) : System task 'dumpvars' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":18)
+WARN  (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":19)
+WARN  (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":20)
+WARN  (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":21)
+WARN  (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":22)
+WARN  (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":23)
+WARN  (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":24)
+WARN  (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":25)
+WARN  (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":26)
+WARN  (EX3858) : System task 'display' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":27)
+WARN  (EX3780) : Using initial value of 'r1' since it is never assigned("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":28)
+Compiling module 'lab2'("C:\cygwin64\home\koray\verilog\lab2\src\lab2.v":1)
+NOTE  (EX0101) : Current top module is "tb"
+WARN  (EX0203) : Top module "tb" has no ports("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+WARN  (NL0002) : The module "lab2" instantiated to "uut" is swept in optimizing("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":12)
+[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
+[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
+GowinSynthesis finish