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rearrangement

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This commit is contained in:
k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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36
iverilog/tobb/labs/lab2/impl/temp/rtl_parser.result Normal file
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[
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
"InstLine" : 1,
"InstName" : "BitM",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
"ModuleLine" : 1,
"ModuleName" : "BitM"
},
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
"InstLine" : 1,
"InstName" : "fullAdder",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
"ModuleLine" : 1,
"ModuleName" : "fullAdder"
},
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
"InstLine" : 1,
"InstName" : "tb",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
"ModuleLine" : 1,
"ModuleName" : "tb",
"SubInsts" : [
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
"InstLine" : 6,
"InstName" : "uut",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v",
"ModuleLine" : 1,
"ModuleName" : "halfAdder"
}
]
}
]