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rearrangement

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k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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202
iverilog/tobb/lab7tetris/a.out Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x5555993ec6a0 .scope module, "tb" "tb" 2 1;
.timescale 0 0;
v0x5555994063f0_0 .net "bitti_mi", 0 0, L_0x5555994068b0; 1 drivers
v0x5555994064b0_0 .net "cevrim", 4 0, L_0x5555994067c0; 1 drivers
v0x555599406550_0 .var "clk", 0 0;
v0x555599406650_0 .var "parca", 2 0;
v0x555599406720_0 .net "yukseklik", 4 0, v0x555599406270_0; 1 drivers
S_0x5555993ec830 .scope module, "uut" "tetris" 2 10, 3 1 0, S_0x5555993ec6a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 3 "parca";
.port_info 2 /OUTPUT 5 "yukseklik";
.port_info 3 /OUTPUT 5 "cevrim";
.port_info 4 /OUTPUT 1 "bitti_mi";
L_0x5555994067c0 .functor BUFZ 5, v0x555599405d00_0, C4<00000>, C4<00000>, C4<00000>;
L_0x7f7b9f218018 .functor BUFT 1, C4<10000>, C4<0>, C4<0>, C4<0>;
v0x5555993ec9e0_0 .net/2u *"_ivl_2", 4 0, L_0x7f7b9f218018; 1 drivers
v0x555599405b80_0 .net "bitti_mi", 0 0, L_0x5555994068b0; alias, 1 drivers
v0x555599405c40_0 .net "cevrim", 4 0, L_0x5555994067c0; alias, 1 drivers
v0x555599405d00_0 .var "cevrim_r", 4 0;
v0x555599405de0_0 .net "clk", 0 0, v0x555599406550_0; 1 drivers
v0x555599405ef0_0 .net "parca", 2 0, v0x555599406650_0; 1 drivers
v0x555599405fd0_0 .var "y_0", 4 0;
v0x5555994060b0_0 .var "y_1", 4 0;
v0x555599406190_0 .var "y_2", 4 0;
v0x555599406270_0 .var "yukseklik", 4 0;
E_0x5555993e7d70 .event posedge, v0x555599405b80_0;
E_0x5555993af500 .event posedge, v0x555599405de0_0;
L_0x5555994068b0 .cmp/eq 5, v0x555599405d00_0, L_0x7f7b9f218018;
.scope S_0x5555993ec830;
T_0 ;
%pushi/vec4 0, 0, 5;
%store/vec4 v0x555599405d00_0, 0, 5;
%pushi/vec4 0, 0, 5;
%store/vec4 v0x555599405fd0_0, 0, 5;
%pushi/vec4 0, 0, 5;
%store/vec4 v0x5555994060b0_0, 0, 5;
%pushi/vec4 0, 0, 5;
%store/vec4 v0x555599406190_0, 0, 5;
%end;
.thread T_0;
.scope S_0x5555993ec830;
T_1 ;
%wait E_0x5555993af500;
%load/vec4 v0x555599405c40_0;
%cmpi/ne 16, 0, 5;
%jmp/0xz T_1.0, 4;
%load/vec4 v0x555599405d00_0;
%addi 1, 0, 5;
%assign/vec4 v0x555599405d00_0, 0;
%load/vec4 v0x555599405fd0_0;
%pushi/vec4 0, 0, 4;
%load/vec4 v0x555599405ef0_0;
%parti/s 1, 0, 2;
%concat/vec4; draw_concat_vec4
%add;
%assign/vec4 v0x555599405fd0_0, 0;
%load/vec4 v0x5555994060b0_0;
%pushi/vec4 0, 0, 4;
%load/vec4 v0x555599405ef0_0;
%parti/s 1, 1, 2;
%concat/vec4; draw_concat_vec4
%add;
%assign/vec4 v0x5555994060b0_0, 0;
%load/vec4 v0x555599406190_0;
%pushi/vec4 0, 0, 4;
%load/vec4 v0x555599405ef0_0;
%parti/s 1, 2, 3;
%concat/vec4; draw_concat_vec4
%add;
%assign/vec4 v0x555599406190_0, 0;
T_1.0 ;
%jmp T_1;
.thread T_1;
.scope S_0x5555993ec830;
T_2 ;
%wait E_0x5555993e7d70;
%load/vec4 v0x5555994060b0_0;
%load/vec4 v0x555599405fd0_0;
%cmp/u;
%jmp/0xz T_2.0, 5;
%load/vec4 v0x555599406190_0;
%load/vec4 v0x555599405fd0_0;
%cmp/u;
%jmp/0xz T_2.2, 5;
%load/vec4 v0x555599405fd0_0;
%assign/vec4 v0x555599406270_0, 0;
%jmp T_2.3;
T_2.2 ;
%load/vec4 v0x555599406190_0;
%assign/vec4 v0x555599406270_0, 0;
T_2.3 ;
%jmp T_2.1;
T_2.0 ;
%load/vec4 v0x5555994060b0_0;
%load/vec4 v0x555599405fd0_0;
%cmp/u;
%jmp/0xz T_2.4, 5;
%load/vec4 v0x555599406190_0;
%load/vec4 v0x5555994060b0_0;
%cmp/u;
%jmp/0xz T_2.6, 5;
%load/vec4 v0x5555994060b0_0;
%assign/vec4 v0x555599406270_0, 0;
%jmp T_2.7;
T_2.6 ;
%load/vec4 v0x555599406190_0;
%assign/vec4 v0x555599406270_0, 0;
T_2.7 ;
T_2.4 ;
T_2.1 ;
%jmp T_2;
.thread T_2;
.scope S_0x5555993ec6a0;
T_3 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x555599406550_0, 0, 1;
%end;
.thread T_3;
.scope S_0x5555993ec6a0;
T_4 ;
%load/vec4 v0x555599406550_0;
%inv;
%store/vec4 v0x555599406550_0, 0, 1;
%delay 5, 0;
%jmp T_4;
.thread T_4;
.scope S_0x5555993ec6a0;
T_5 ;
%vpi_call 2 23 "$dumpvars" {0 0 0};
%pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0;
%vpi_call 2 42 "$finish" {0 0 0};
%end;
.thread T_5;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tb.v";
"tetris.v";

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Model implementation (design independent parts)
#include "Vtb.h"
#include "Vtb__Syms.h"
//============================================================
// Constructors
Vtb::Vtb(VerilatedContext* _vcontextp__, const char* _vcname__)
: VerilatedModel{*_vcontextp__}
, vlSymsp{new Vtb__Syms(contextp(), _vcname__, this)}
, rootp{&(vlSymsp->TOP)}
{
// Register model with the context
contextp()->addModel(this);
}
Vtb::Vtb(const char* _vcname__)
: Vtb(Verilated::threadContextp(), _vcname__)
{
}
//============================================================
// Destructor
Vtb::~Vtb() {
delete vlSymsp;
}
//============================================================
// Evaluation function
#ifdef VL_DEBUG
void Vtb___024root___eval_debug_assertions(Vtb___024root* vlSelf);
#endif // VL_DEBUG
void Vtb___024root___eval_static(Vtb___024root* vlSelf);
void Vtb___024root___eval_initial(Vtb___024root* vlSelf);
void Vtb___024root___eval_settle(Vtb___024root* vlSelf);
void Vtb___024root___eval(Vtb___024root* vlSelf);
void Vtb::eval_step() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vtb::eval_step\n"); );
#ifdef VL_DEBUG
// Debug assertions
Vtb___024root___eval_debug_assertions(&(vlSymsp->TOP));
#endif // VL_DEBUG
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {
vlSymsp->__Vm_didInit = true;
VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n"););
Vtb___024root___eval_static(&(vlSymsp->TOP));
Vtb___024root___eval_initial(&(vlSymsp->TOP));
Vtb___024root___eval_settle(&(vlSymsp->TOP));
}
// MTask 0 start
VL_DEBUG_IF(VL_DBG_MSGF("MTask0 starting\n"););
Verilated::mtaskId(0);
VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n"););
Vtb___024root___eval(&(vlSymsp->TOP));
// Evaluate cleanup
Verilated::endOfThreadMTask(vlSymsp->__Vm_evalMsgQp);
Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);
}
//============================================================
// Events and timing
bool Vtb::eventsPending() { return !vlSymsp->TOP.__VdlySched.empty(); }
uint64_t Vtb::nextTimeSlot() { return vlSymsp->TOP.__VdlySched.nextTimeSlot(); }
//============================================================
// Utilities
const char* Vtb::name() const {
return vlSymsp->name();
}
//============================================================
// Invoke final blocks
void Vtb___024root___eval_final(Vtb___024root* vlSelf);
VL_ATTR_COLD void Vtb::final() {
Vtb___024root___eval_final(&(vlSymsp->TOP));
}
//============================================================
// Implementations of abstract methods from VerilatedModel
const char* Vtb::hierName() const { return vlSymsp->name(); }
const char* Vtb::modelName() const { return "Vtb"; }
unsigned Vtb::threads() const { return 1; }

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary model header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef VERILATED_VTB_H_
#define VERILATED_VTB_H_ // guard
#include "verilated.h"
class Vtb__Syms;
class Vtb___024root;
// This class is the main interface to the Verilated model
class Vtb VL_NOT_FINAL : public VerilatedModel {
private:
// Symbol table holding complete model state (owned by this class)
Vtb__Syms* const vlSymsp;
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
// CELLS
// Public to allow access to /* verilator public */ items.
// Otherwise the application code can consider these internals.
// Root instance pointer to allow access to model internals,
// including inlined /* verilator public_flat_* */ items.
Vtb___024root* const rootp;
// CONSTRUCTORS
/// Construct the model; called by application code
/// If contextp is null, then the model will use the default global context
/// If name is "", then makes a wrapper with a
/// single model invisible with respect to DPI scope names.
explicit Vtb(VerilatedContext* contextp, const char* name = "TOP");
explicit Vtb(const char* name = "TOP");
/// Destroy the model; called (often implicitly) by application code
virtual ~Vtb();
private:
VL_UNCOPYABLE(Vtb); ///< Copying not allowed
public:
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval() { eval_step(); }
/// Evaluate when calling multiple units/models per time step.
void eval_step();
/// Evaluate at end of a timestep for tracing, when using eval_step().
/// Application must call after all eval() and before time changes.
void eval_end_step() {}
/// Simulation complete, run final blocks. Application must call on completion.
void final();
/// Are there scheduled events to handle?
bool eventsPending();
/// Returns time at next time slot. Aborts if !eventsPending()
uint64_t nextTimeSlot();
/// Retrieve name of this model instance (as passed to constructor).
const char* name() const;
// Abstract methods from VerilatedModel
const char* hierName() const override final;
const char* modelName() const override final;
unsigned threads() const override final;
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
#endif // guard

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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vtb.mk
default: Vtb
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# C++ code coverage 0/1 (from --prof-c)
VM_PROFC = 0
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vtb
# Module prefix (from --prefix)
VM_MODPREFIX = Vtb
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-DVL_TIME_CONTEXT \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
### Default rules...
# Include list of all generated classes
include Vtb_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
### Link rules... (from --exe)
Vtb: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a $(VM_HIER_LIBS)
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@
# Verilated -*- Makefile -*-

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// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vtb.cpp"
#include "Vtb___024root__DepSet_hfe20aad3__0.cpp"
#include "Vtb___024root__DepSet_ha183790c__0.cpp"
#include "Vtb__main.cpp"
#include "Vtb___024root__Slow.cpp"
#include "Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp"
#include "Vtb___024root__DepSet_ha183790c__0__Slow.cpp"
#include "Vtb__Syms.cpp"

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Vtb__ALL.o: Vtb__ALL.cpp Vtb.cpp Vtb.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_types.h \
/usr/share/verilator/include/verilated_funcs.h Vtb__Syms.h \
Vtb___024root.h /usr/share/verilator/include/verilated_timing.h \
/usr/share/verilator/include/verilated.h \
Vtb___024root__DepSet_hfe20aad3__0.cpp \
Vtb___024root__DepSet_ha183790c__0.cpp Vtb__main.cpp \
Vtb___024root__Slow.cpp Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp \
Vtb___024root__DepSet_ha183790c__0__Slow.cpp Vtb__Syms.cpp

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vtb__Syms.h"
#include "Vtb.h"
#include "Vtb___024root.h"
// FUNCTIONS
Vtb__Syms::~Vtb__Syms()
{
}
Vtb__Syms::Vtb__Syms(VerilatedContext* contextp, const char* namep, Vtb* modelp)
: VerilatedSyms{contextp}
// Setup internal state of the Syms class
, __Vm_modelp{modelp}
// Setup module instances
, TOP{this, namep}
{
// Configure time unit / time precision
_vm_contextp__->timeunit(-12);
_vm_contextp__->timeprecision(-12);
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOP.__Vconfigure(true);
}

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header,
// unless using verilator public meta comments.
#ifndef VERILATED_VTB__SYMS_H_
#define VERILATED_VTB__SYMS_H_ // guard
#include "verilated.h"
// INCLUDE MODEL CLASS
#include "Vtb.h"
// INCLUDE MODULE CLASSES
#include "Vtb___024root.h"
// SYMS CLASS (contains all model state)
class Vtb__Syms final : public VerilatedSyms {
public:
// INTERNAL STATE
Vtb* const __Vm_modelp;
bool __Vm_didInit = false;
// MODULE INSTANCE STATE
Vtb___024root TOP;
// CONSTRUCTORS
Vtb__Syms(VerilatedContext* contextp, const char* namep, Vtb* modelp);
~Vtb__Syms();
// METHODS
const char* name() { return TOP.name(); }
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
#endif // guard

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vtb.h for the primary calling header
#ifndef VERILATED_VTB___024ROOT_H_
#define VERILATED_VTB___024ROOT_H_ // guard
#include "verilated.h"
#include "verilated_timing.h"
class Vtb__Syms;
class Vtb___024root final : public VerilatedModule {
public:
// DESIGN SPECIFIC STATE
CData/*0:0*/ tb__DOT__clk;
CData/*0:0*/ tb__DOT__bitti_mi;
CData/*2:0*/ tb__DOT__parca;
CData/*4:0*/ tb__DOT__yukseklik;
CData/*4:0*/ tb__DOT__cevrim;
CData/*4:0*/ tb__DOT__uut__DOT__cevrim_r;
CData/*4:0*/ tb__DOT__uut__DOT__y_0;
CData/*4:0*/ tb__DOT__uut__DOT__y_1;
CData/*4:0*/ tb__DOT__uut__DOT__y_2;
CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_0;
CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_1;
CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_2;
CData/*0:0*/ __Vtrigrprev__TOP__tb__DOT__clk;
CData/*0:0*/ __Vtrigrprev__TOP__tb__DOT__bitti_mi;
CData/*0:0*/ __VactContinue;
IData/*31:0*/ __VstlIterCount;
IData/*31:0*/ __VactIterCount;
VlDelayScheduler __VdlySched;
VlTriggerVec<1> __VstlTriggered;
VlTriggerVec<3> __VactTriggered;
VlTriggerVec<3> __VnbaTriggered;
// INTERNAL VARIABLES
Vtb__Syms* const vlSymsp;
// CONSTRUCTORS
Vtb___024root(Vtb__Syms* symsp, const char* v__name);
~Vtb___024root();
VL_UNCOPYABLE(Vtb___024root);
// INTERNAL METHODS
void __Vconfigure(bool first);
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
#endif // guard

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vtb.h for the primary calling header
#include "verilated.h"
#include "Vtb___024root.h"
VlCoroutine Vtb___024root___eval_initial__TOP__0(Vtb___024root* vlSelf);
void Vtb___024root___eval_initial(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_initial\n"); );
// Body
Vtb___024root___eval_initial__TOP__0(vlSelf);
vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = vlSelf->tb__DOT__clk;
vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = vlSelf->tb__DOT__bitti_mi;
}
VL_INLINE_OPT VlCoroutine Vtb___024root___eval_initial__TOP__0(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_initial__TOP__0\n"); );
// Body
while (1U) {
co_await vlSelf->__VdlySched.delay(5U, "tb.v",
20);
vlSelf->tb__DOT__clk = (1U & (~ (IData)(vlSelf->tb__DOT__clk)));
}
vlSelf->tb__DOT__parca = 5U;
co_await vlSelf->__VdlySched.delay(0xc8U, "tb.v",
21);
VL_WRITEF("%2#\n%2#\n%1#\n",5,vlSelf->tb__DOT__yukseklik,
5,(IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r),
1,vlSelf->tb__DOT__bitti_mi);
VL_FINISH_MT("tb.v", 25, "");
}
void Vtb___024root___eval_act(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_act\n"); );
}
VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__0(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__0\n"); );
// Body
vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = vlSelf->tb__DOT__uut__DOT__y_2;
vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = vlSelf->tb__DOT__uut__DOT__y_1;
vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = vlSelf->tb__DOT__uut__DOT__y_0;
if ((0x10U != (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r))) {
vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = (0x1fU
& ((IData)(vlSelf->tb__DOT__uut__DOT__y_2)
+
(1U
& ((IData)(vlSelf->tb__DOT__parca)
>> 2U))));
vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = (0x1fU
& ((IData)(vlSelf->tb__DOT__uut__DOT__y_1)
+
(1U
& ((IData)(vlSelf->tb__DOT__parca)
>> 1U))));
vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = (0x1fU
& ((IData)(vlSelf->tb__DOT__uut__DOT__y_0)
+
(1U
& (IData)(vlSelf->tb__DOT__parca))));
}
if ((0x10U != (IData)(vlSelf->tb__DOT__cevrim))) {
vlSelf->tb__DOT__uut__DOT__cevrim_r = (0x1fU
& ((IData)(1U)
+ (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r)));
}
vlSelf->tb__DOT__cevrim = vlSelf->tb__DOT__uut__DOT__cevrim_r;
vlSelf->tb__DOT__bitti_mi = (0x10U == (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r));
}
VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__1(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__1\n"); );
// Body
if (((IData)(vlSelf->tb__DOT__uut__DOT__y_0) > (IData)(vlSelf->tb__DOT__uut__DOT__y_1))) {
vlSelf->tb__DOT__yukseklik = (((IData)(vlSelf->tb__DOT__uut__DOT__y_0)
> (IData)(vlSelf->tb__DOT__uut__DOT__y_2))
? (IData)(vlSelf->tb__DOT__uut__DOT__y_0)
: (IData)(vlSelf->tb__DOT__uut__DOT__y_2));
} else if (((IData)(vlSelf->tb__DOT__uut__DOT__y_0)
> (IData)(vlSelf->tb__DOT__uut__DOT__y_1))) {
vlSelf->tb__DOT__yukseklik = (((IData)(vlSelf->tb__DOT__uut__DOT__y_1)
> (IData)(vlSelf->tb__DOT__uut__DOT__y_2))
? (IData)(vlSelf->tb__DOT__uut__DOT__y_1)
: (IData)(vlSelf->tb__DOT__uut__DOT__y_2));
}
}
VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__2(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__2\n"); );
// Body
vlSelf->tb__DOT__uut__DOT__y_0 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_0;
vlSelf->tb__DOT__uut__DOT__y_1 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_1;
vlSelf->tb__DOT__uut__DOT__y_2 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_2;
}
void Vtb___024root___eval_nba(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_nba\n"); );
// Body
if (vlSelf->__VnbaTriggered.at(0U)) {
Vtb___024root___nba_sequent__TOP__0(vlSelf);
}
if (vlSelf->__VnbaTriggered.at(1U)) {
Vtb___024root___nba_sequent__TOP__1(vlSelf);
}
if (vlSelf->__VnbaTriggered.at(0U)) {
Vtb___024root___nba_sequent__TOP__2(vlSelf);
}
}
void Vtb___024root___eval_triggers__act(Vtb___024root* vlSelf);
#ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf);
#endif // VL_DEBUG
void Vtb___024root___timing_resume(Vtb___024root* vlSelf);
#ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__nba(Vtb___024root* vlSelf);
#endif // VL_DEBUG
void Vtb___024root___eval(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval\n"); );
// Init
VlTriggerVec<3> __VpreTriggered;
IData/*31:0*/ __VnbaIterCount;
CData/*0:0*/ __VnbaContinue;
// Body
__VnbaIterCount = 0U;
__VnbaContinue = 1U;
while (__VnbaContinue) {
__VnbaContinue = 0U;
vlSelf->__VnbaTriggered.clear();
vlSelf->__VactIterCount = 0U;
vlSelf->__VactContinue = 1U;
while (vlSelf->__VactContinue) {
vlSelf->__VactContinue = 0U;
Vtb___024root___eval_triggers__act(vlSelf);
if (vlSelf->__VactTriggered.any()) {
vlSelf->__VactContinue = 1U;
if (VL_UNLIKELY((0x64U < vlSelf->__VactIterCount))) {
#ifdef VL_DEBUG
Vtb___024root___dump_triggers__act(vlSelf);
#endif
VL_FATAL_MT("tb.v", 1, "", "Active region did not converge.");
}
vlSelf->__VactIterCount = ((IData)(1U)
+ vlSelf->__VactIterCount);
__VpreTriggered.andNot(vlSelf->__VactTriggered, vlSelf->__VnbaTriggered);
vlSelf->__VnbaTriggered.set(vlSelf->__VactTriggered);
Vtb___024root___timing_resume(vlSelf);
Vtb___024root___eval_act(vlSelf);
}
}
if (vlSelf->__VnbaTriggered.any()) {
__VnbaContinue = 1U;
if (VL_UNLIKELY((0x64U < __VnbaIterCount))) {
#ifdef VL_DEBUG
Vtb___024root___dump_triggers__nba(vlSelf);
#endif
VL_FATAL_MT("tb.v", 1, "", "NBA region did not converge.");
}
__VnbaIterCount = ((IData)(1U) + __VnbaIterCount);
Vtb___024root___eval_nba(vlSelf);
}
}
}
void Vtb___024root___timing_resume(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___timing_resume\n"); );
// Body
if (vlSelf->__VactTriggered.at(2U)) {
vlSelf->__VdlySched.resume();
}
}
#ifdef VL_DEBUG
void Vtb___024root___eval_debug_assertions(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_debug_assertions\n"); );
}
#endif // VL_DEBUG

165
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vtb.h for the primary calling header
#include "verilated.h"
#include "Vtb___024root.h"
VL_ATTR_COLD void Vtb___024root___eval_static__TOP(Vtb___024root* vlSelf);
VL_ATTR_COLD void Vtb___024root___eval_static(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_static\n"); );
// Body
Vtb___024root___eval_static__TOP(vlSelf);
}
VL_ATTR_COLD void Vtb___024root___eval_static__TOP(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_static__TOP\n"); );
// Body
vlSelf->tb__DOT__clk = 0U;
vlSelf->tb__DOT__uut__DOT__cevrim_r = 0U;
vlSelf->tb__DOT__uut__DOT__y_0 = 0U;
vlSelf->tb__DOT__uut__DOT__y_1 = 0U;
vlSelf->tb__DOT__uut__DOT__y_2 = 0U;
}
VL_ATTR_COLD void Vtb___024root___eval_final(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_final\n"); );
}
VL_ATTR_COLD void Vtb___024root___eval_triggers__stl(Vtb___024root* vlSelf);
#ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf);
#endif // VL_DEBUG
VL_ATTR_COLD void Vtb___024root___eval_stl(Vtb___024root* vlSelf);
VL_ATTR_COLD void Vtb___024root___eval_settle(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_settle\n"); );
// Init
CData/*0:0*/ __VstlContinue;
// Body
vlSelf->__VstlIterCount = 0U;
__VstlContinue = 1U;
while (__VstlContinue) {
__VstlContinue = 0U;
Vtb___024root___eval_triggers__stl(vlSelf);
if (vlSelf->__VstlTriggered.any()) {
__VstlContinue = 1U;
if (VL_UNLIKELY((0x64U < vlSelf->__VstlIterCount))) {
#ifdef VL_DEBUG
Vtb___024root___dump_triggers__stl(vlSelf);
#endif
VL_FATAL_MT("tb.v", 1, "", "Settle region did not converge.");
}
vlSelf->__VstlIterCount = ((IData)(1U)
+ vlSelf->__VstlIterCount);
Vtb___024root___eval_stl(vlSelf);
}
}
}
#ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__stl\n"); );
// Body
if ((1U & (~ (IData)(vlSelf->__VstlTriggered.any())))) {
VL_DBG_MSGF(" No triggers active\n");
}
if (vlSelf->__VstlTriggered.at(0U)) {
VL_DBG_MSGF(" 'stl' region trigger index 0 is active: Internal 'stl' trigger - first iteration\n");
}
}
#endif // VL_DEBUG
VL_ATTR_COLD void Vtb___024root___stl_sequent__TOP__0(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___stl_sequent__TOP__0\n"); );
// Body
vlSelf->tb__DOT__cevrim = vlSelf->tb__DOT__uut__DOT__cevrim_r;
vlSelf->tb__DOT__bitti_mi = (0x10U == (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r));
}
VL_ATTR_COLD void Vtb___024root___eval_stl(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_stl\n"); );
// Body
if (vlSelf->__VstlTriggered.at(0U)) {
Vtb___024root___stl_sequent__TOP__0(vlSelf);
}
}
#ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__act\n"); );
// Body
if ((1U & (~ (IData)(vlSelf->__VactTriggered.any())))) {
VL_DBG_MSGF(" No triggers active\n");
}
if (vlSelf->__VactTriggered.at(0U)) {
VL_DBG_MSGF(" 'act' region trigger index 0 is active: @(posedge tb.clk)\n");
}
if (vlSelf->__VactTriggered.at(1U)) {
VL_DBG_MSGF(" 'act' region trigger index 1 is active: @(posedge tb.bitti_mi)\n");
}
if (vlSelf->__VactTriggered.at(2U)) {
VL_DBG_MSGF(" 'act' region trigger index 2 is active: @([true] __VdlySched.awaitingCurrentTime())\n");
}
}
#endif // VL_DEBUG
#ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__nba(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__nba\n"); );
// Body
if ((1U & (~ (IData)(vlSelf->__VnbaTriggered.any())))) {
VL_DBG_MSGF(" No triggers active\n");
}
if (vlSelf->__VnbaTriggered.at(0U)) {
VL_DBG_MSGF(" 'nba' region trigger index 0 is active: @(posedge tb.clk)\n");
}
if (vlSelf->__VnbaTriggered.at(1U)) {
VL_DBG_MSGF(" 'nba' region trigger index 1 is active: @(posedge tb.bitti_mi)\n");
}
if (vlSelf->__VnbaTriggered.at(2U)) {
VL_DBG_MSGF(" 'nba' region trigger index 2 is active: @([true] __VdlySched.awaitingCurrentTime())\n");
}
}
#endif // VL_DEBUG
VL_ATTR_COLD void Vtb___024root___ctor_var_reset(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___ctor_var_reset\n"); );
// Body
vlSelf->tb__DOT__parca = VL_RAND_RESET_I(3);
vlSelf->tb__DOT__clk = VL_RAND_RESET_I(1);
vlSelf->tb__DOT__yukseklik = VL_RAND_RESET_I(5);
vlSelf->tb__DOT__cevrim = VL_RAND_RESET_I(5);
vlSelf->tb__DOT__bitti_mi = VL_RAND_RESET_I(1);
vlSelf->tb__DOT__uut__DOT__cevrim_r = VL_RAND_RESET_I(5);
vlSelf->tb__DOT__uut__DOT__y_0 = VL_RAND_RESET_I(5);
vlSelf->tb__DOT__uut__DOT__y_1 = VL_RAND_RESET_I(5);
vlSelf->tb__DOT__uut__DOT__y_2 = VL_RAND_RESET_I(5);
vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = VL_RAND_RESET_I(5);
vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = VL_RAND_RESET_I(5);
vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = VL_RAND_RESET_I(5);
vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = VL_RAND_RESET_I(1);
vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = VL_RAND_RESET_I(1);
}

31
iverilog/tobb/lab7tetris/obj_dir/Vtb___024root__DepSet_hfe20aad3__0.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vtb.h for the primary calling header
#include "verilated.h"
#include "Vtb__Syms.h"
#include "Vtb___024root.h"
#ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf);
#endif // VL_DEBUG
void Vtb___024root___eval_triggers__act(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_triggers__act\n"); );
// Body
vlSelf->__VactTriggered.at(0U) = ((IData)(vlSelf->tb__DOT__clk)
& (~ (IData)(vlSelf->__Vtrigrprev__TOP__tb__DOT__clk)));
vlSelf->__VactTriggered.at(1U) = ((IData)(vlSelf->tb__DOT__bitti_mi)
& (~ (IData)(vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi)));
vlSelf->__VactTriggered.at(2U) = vlSelf->__VdlySched.awaitingCurrentTime();
vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = vlSelf->tb__DOT__clk;
vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = vlSelf->tb__DOT__bitti_mi;
#ifdef VL_DEBUG
if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
Vtb___024root___dump_triggers__act(vlSelf);
}
#endif
}

25
iverilog/tobb/lab7tetris/obj_dir/Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vtb.h for the primary calling header
#include "verilated.h"
#include "Vtb__Syms.h"
#include "Vtb___024root.h"
#ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf);
#endif // VL_DEBUG
VL_ATTR_COLD void Vtb___024root___eval_triggers__stl(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_triggers__stl\n"); );
// Body
vlSelf->__VstlTriggered.at(0U) = (0U == vlSelf->__VstlIterCount);
#ifdef VL_DEBUG
if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
Vtb___024root___dump_triggers__stl(vlSelf);
}
#endif
}

26
iverilog/tobb/lab7tetris/obj_dir/Vtb___024root__Slow.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vtb.h for the primary calling header
#include "verilated.h"
#include "Vtb__Syms.h"
#include "Vtb___024root.h"
void Vtb___024root___ctor_var_reset(Vtb___024root* vlSelf);
Vtb___024root::Vtb___024root(Vtb__Syms* symsp, const char* v__name)
: VerilatedModule{v__name}
, __VdlySched{*symsp->_vm_contextp__}
, vlSymsp{symsp}
{
// Reset structure values
Vtb___024root___ctor_var_reset(this);
}
void Vtb___024root::__Vconfigure(bool first) {
if (false && first) {} // Prevent unused
}
Vtb___024root::~Vtb___024root() {
}

34
iverilog/tobb/lab7tetris/obj_dir/Vtb__main.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: main() calling loop, created with Verilator --main
#include "verilated.h"
#include "Vtb.h"
//======================
int main(int argc, char** argv, char**) {
// Setup context, defaults, and parse command line
Verilated::debug(0);
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
contextp->commandArgs(argc, argv);
// Construct the Verilated model, from Vtop.h generated from Verilating
const std::unique_ptr<Vtb> topp{new Vtb{contextp.get()}};
// Simulate until $finish
while (!contextp->gotFinish()) {
// Evaluate model
topp->eval();
// Advance time
if (!topp->eventsPending()) break;
contextp->time(topp->nextTimeSlot());
}
if (!contextp->gotFinish()) {
VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
}
// Final model cleanup
topp->final();
return 0;
}

1
iverilog/tobb/lab7tetris/obj_dir/Vtb__ver.d Normal file
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@ -0,0 +1 @@
obj_dir/Vtb.cpp obj_dir/Vtb.h obj_dir/Vtb.mk obj_dir/Vtb__Syms.cpp obj_dir/Vtb__Syms.h obj_dir/Vtb___024root.h obj_dir/Vtb___024root__DepSet_ha183790c__0.cpp obj_dir/Vtb___024root__DepSet_ha183790c__0__Slow.cpp obj_dir/Vtb___024root__DepSet_hfe20aad3__0.cpp obj_dir/Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp obj_dir/Vtb___024root__Slow.cpp obj_dir/Vtb__main.cpp obj_dir/Vtb__ver.d obj_dir/Vtb_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin tb.v tetris.v

20
iverilog/tobb/lab7tetris/obj_dir/Vtb__verFiles.dat Normal file
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# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--binary tb.v tetris.v --timing"
S 12244816 28045 1719496600 881980186 1680199511 0 "/usr/bin/verilator_bin"
T 2837 6675 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb.cpp"
T 2631 6439 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb.h"
T 1722 7381 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb.mk"
T 730 216 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb__Syms.cpp"
T 884 225 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb__Syms.h"
T 1524 6695 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root.h"
T 9237 7333 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root__DepSet_ha183790c__0.cpp"
T 6922 7184 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root__DepSet_ha183790c__0__Slow.cpp"
T 1304 7283 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root__DepSet_hfe20aad3__0.cpp"
T 823 7044 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp"
T 644 6712 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root__Slow.cpp"
T 955 7337 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb__main.cpp"
T 471 7389 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb__ver.d"
T 0 0 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb__verFiles.dat"
T 1646 7340 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb_classes.mk"
S 376 233 1720894754 765684145 1720894754 765684145 "tb.v"
S 820 230 1720894095 565675203 1720894095 565675203 "tetris.v"

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iverilog/tobb/lab7tetris/obj_dir/Vtb_classes.mk Normal file
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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vtb.mk for the caller.
### Switches...
# C11 constructs required? 0/1 (always on now)
VM_C11 = 1
# Timing enabled? 0/1
VM_TIMING = 1
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Parallel builds? 0/1 (from --output-split)
VM_PARALLEL_BUILDS = 0
# Tracing output mode? 0/1 (from --trace/--trace-fst)
VM_TRACE = 0
# Tracing output mode in VCD format? 0/1 (from --trace)
VM_TRACE_VCD = 0
# Tracing output mode in FST format? 0/1 (from --trace-fst)
VM_TRACE_FST = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vtb \
Vtb___024root__DepSet_hfe20aad3__0 \
Vtb___024root__DepSet_ha183790c__0 \
Vtb__main \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
Vtb___024root__Slow \
Vtb___024root__DepSet_hfe20aad3__0__Slow \
Vtb___024root__DepSet_ha183790c__0__Slow \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vtb__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
verilated_timing \
verilated_threads \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

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verilated.o: /usr/share/verilator/include/verilated.cpp \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_imp.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_types.h \
/usr/share/verilator/include/verilated_funcs.h \
/usr/share/verilator/include/verilated_syms.h \
/usr/share/verilator/include/verilated_sym_props.h \
/usr/share/verilator/include/verilated_threads.h \
/usr/share/verilator/include/verilated_trace.h \
/usr/share/verilator/include/verilated_trace_defs.h

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verilated_threads.o: /usr/share/verilator/include/verilated_threads.cpp \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_threads.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_types.h \
/usr/share/verilator/include/verilated_funcs.h

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iverilog/tobb/lab7tetris/obj_dir/verilated_timing.d Normal file
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verilated_timing.o: /usr/share/verilator/include/verilated_timing.cpp \
/usr/share/verilator/include/verilated_timing.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_types.h \
/usr/share/verilator/include/verilated_funcs.h

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iverilog/tobb/lab7tetris/run.sh Normal file
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iverilog *.v && vvp a.out
if [ -f "dump.vcd" ]; then
gtkwave dump.vcd
rm dump.vcd
fi

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iverilog/tobb/lab7tetris/tb.v Normal file
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module tb();
reg [2:0] parca;
reg clk = 0;
wire [4:0] yukseklik;
wire [4:0] cevrim;
wire bitti_mi;
tetris uut(
.parca(parca),
.clk(clk),
.yukseklik(yukseklik),
.cevrim(cevrim),
.bitti_mi(bitti_mi)
);
always begin
clk = ~clk; #5;
end
initial begin
$dumpvars;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
$finish;
end
endmodule

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iverilog/tobb/lab7tetris/tetris.v Normal file
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module tetris(
input clk,
input [2:0] parca,
output reg [4:0] yukseklik,
output [4:0] cevrim,
output bitti_mi
);
reg [4:0] cevrim_r = 0;
reg [4:0] y_0 = 0;
reg [4:0] y_1 = 0;
reg [4:0] y_2 = 0;
assign cevrim = cevrim_r;
assign bitti_mi = cevrim_r == 5'b10000;
always @(posedge clk) begin
if (cevrim != 5'b10000) begin
cevrim_r <= cevrim_r + 5'd1;
y_0 <= y_0 + {4'b0000, parca[0]};
y_1 <= y_1 + {4'b0000, parca[1]};
y_2 <= y_2 + {4'b0000, parca[2]};
end
end
/* always @(posedge bitti_mi)
yukseklik <= y_0 > y_1
? y_0 > y_2 ? y_0 : y_2
: y_1 > y_2 ? y_1 : y_2;
*/
always @(posedge bitti_mi) begin
if (y_0 > y_1) begin
if (y_0 > y_2) yukseklik <= y_0;
else yukseklik <= y_2;
end else if (y_0 > y_1) begin
if (y_1 > y_2) yukseklik <= y_1;
else yukseklik <= y_2;
end
end
endmodule