rearrangement

iverilog/tobb/lab2/fdmp.vcd

@@ -0,0 +1,84 @@
+$date
+	Tue Oct  8 14:05:40 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module fulladdertb $end
+$var wire 1 ! w2 $end
+$var wire 1 " w1 $end
+$var reg 1 # r1 $end
+$var reg 1 $ r2 $end
+$var reg 1 % r3 $end
+$scope module uut $end
+$var wire 1 # A $end
+$var wire 1 $ B $end
+$var wire 1 % Cin $end
+$var wire 1 ! Cout $end
+$var wire 1 " S $end
+$var wire 1 & AxB $end
+$var wire 1 ' AnB2 $end
+$var wire 1 ( AnB1 $end
+$scope module h1 $end
+$var wire 1 # A $end
+$var wire 1 $ B $end
+$var wire 1 ' C $end
+$var wire 1 & S $end
+$upscope $end
+$scope module h2 $end
+$var wire 1 & A $end
+$var wire 1 % B $end
+$var wire 1 ( C $end
+$var wire 1 " S $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0(
+0'
+0&
+0%
+0$
+0#
+0"
+0!
+$end
+#10
+1"
+1%
+#20
+1&
+0%
+1$
+#30
+1!
+0"
+1(
+1%
+#40
+0!
+1"
+0(
+0%
+0$
+1#
+#50
+1!
+0"
+1(
+1%
+#60
+0(
+0&
+1'
+0%
+1$
+#70
+1"
+1%
+#80