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rearrangement

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This commit is contained in:
k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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72
gowin/seq_light_test/src/seqBlink.v
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@ -1,36 +1,36 @@
module seqBlink (
input clock,
output reg [3:0] led
);
reg [2:0] fsm = 0;
reg [31:0] clkcnt = 0;
reg newclk = 0;
always@(posedge clock) begin
clkcnt <= clkcnt + 1'b1;
if (clkcnt > 9_000_000) begin
clkcnt <= 0;
newclk <= ~newclk;
end
end
always@(posedge newclk) begin
if (fsm == 3'd6) begin
fsm <= 0;
end else begin
fsm <= fsm + 1;
end
case (fsm)
3'b000 : led <= 4'b0111;
3'b001 : led <= 4'b1011;
3'b010 : led <= 4'b1101;
3'b011 : led <= 4'b1110;
3'b100 : led <= 4'b1101;
3'b101 : led <= 4'b1011;
3'b110 : led <= 4'b0111;
default: led <= 4'b0000;
endcase
end
endmodule
module seqBlink (
input clock,
output reg [3:0] led
);
reg [2:0] fsm = 0;
reg [31:0] clkcnt = 0;
reg newclk = 0;
always@(posedge clock) begin
clkcnt <= clkcnt + 1'b1;
if (clkcnt > 9_000_000) begin
clkcnt <= 0;
newclk <= ~newclk;
end
end
always@(posedge newclk) begin
if (fsm == 3'd6) begin
fsm <= 0;
end else begin
fsm <= fsm + 1;
end
case (fsm)
3'b000 : led <= 4'b0111;
3'b001 : led <= 4'b1011;
3'b010 : led <= 4'b1101;
3'b011 : led <= 4'b1110;
3'b100 : led <= 4'b1101;
3'b101 : led <= 4'b1011;
3'b110 : led <= 4'b0111;
default: led <= 4'b0000;
endcase
end
endmodule

46
gowin/seq_light_test/src/seqBlinkTB.v
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@ -1,24 +1,24 @@
module seqBlinkTB();
reg clock;
wire [3:0] leds;
seqBlink uut(clock, leds);
initial begin
clock = 0;
end
always begin
clock = ~clock; #5;
end
initial begin
$dumpfile("lab5v.vcd");
$dumpvars;
#100;
$finish;
end
module seqBlinkTB();
reg clock;
wire [3:0] leds;
seqBlink uut(clock, leds);
initial begin
clock = 0;
end
always begin
clock = ~clock; #5;
end
initial begin
$dumpfile("lab5v.vcd");
$dumpvars;
#100;
$finish;
end
endmodule

38
gowin/seq_light_test/src/seq_light_test.cst
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@ -1,19 +1,19 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Sun 07 07 15:26:30 2024
IO_LOC "led[3]" L16;
IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[2]" L14;
IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[1]" N14;
IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[0]" N16;
IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clock" H11;
IO_PORT "clock" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Sun 07 07 15:26:30 2024
IO_LOC "led[3]" L16;
IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[2]" L14;
IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[1]" N14;
IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[0]" N16;
IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clock" H11;
IO_PORT "clock" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;