rearrangement

2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
--- a/gowin/fpga_project/impl/temp/rtl_parser.result
+++ b/gowin/fpga_project/impl/temp/rtl_parser.result
@@ -1,82 +1,82 @@
-[
- {
-  "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
-  "InstLine" : 1,
-  "InstName" : "ledTest",
-  "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
-  "ModuleLine" : 1,
-  "ModuleName" : "ledTest",
-  "SubInsts" : [
-   {
-    "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
-    "InstLine" : 8,
-    "InstName" : "adder",
-    "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
-    "ModuleLine" : 1,
-    "ModuleName" : "bit3adder",
-    "SubInsts" : [
-     {
-      "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
-      "InstLine" : 9,
-      "InstName" : "ha0",
-      "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
-      "ModuleLine" : 1,
-      "ModuleName" : "halfadder"
-     },
-     {
-      "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
-      "InstLine" : 10,
-      "InstName" : "fa0",
-      "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
-      "ModuleLine" : 1,
-      "ModuleName" : "fulladder",
-      "SubInsts" : [
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
-        "InstLine" : 8,
-        "InstName" : "ha1",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "halfadder"
-       },
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
-        "InstLine" : 9,
-        "InstName" : "ha2",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "halfadder"
-       }
-      ]
-     },
-     {
-      "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
-      "InstLine" : 11,
-      "InstName" : "fa1",
-      "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
-      "ModuleLine" : 1,
-      "ModuleName" : "fulladder",
-      "SubInsts" : [
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
-        "InstLine" : 8,
-        "InstName" : "ha1",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "halfadder"
-       },
-       {
-        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
-        "InstLine" : 9,
-        "InstName" : "ha2",
-        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
-        "ModuleLine" : 1,
-        "ModuleName" : "halfadder"
-       }
-      ]
-     }
-    ]
-   }
-  ]
- }
+[
+ {
+  "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
+  "InstLine" : 1,
+  "InstName" : "ledTest",
+  "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
+  "ModuleLine" : 1,
+  "ModuleName" : "ledTest",
+  "SubInsts" : [
+   {
+    "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
+    "InstLine" : 8,
+    "InstName" : "adder",
+    "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
+    "ModuleLine" : 1,
+    "ModuleName" : "bit3adder",
+    "SubInsts" : [
+     {
+      "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
+      "InstLine" : 9,
+      "InstName" : "ha0",
+      "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
+      "ModuleLine" : 1,
+      "ModuleName" : "halfadder"
+     },
+     {
+      "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
+      "InstLine" : 10,
+      "InstName" : "fa0",
+      "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
+      "ModuleLine" : 1,
+      "ModuleName" : "fulladder",
+      "SubInsts" : [
+       {
+        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
+        "InstLine" : 8,
+        "InstName" : "ha1",
+        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
+        "ModuleLine" : 1,
+        "ModuleName" : "halfadder"
+       },
+       {
+        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
+        "InstLine" : 9,
+        "InstName" : "ha2",
+        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
+        "ModuleLine" : 1,
+        "ModuleName" : "halfadder"
+       }
+      ]
+     },
+     {
+      "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
+      "InstLine" : 11,
+      "InstName" : "fa1",
+      "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
+      "ModuleLine" : 1,
+      "ModuleName" : "fulladder",
+      "SubInsts" : [
+       {
+        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
+        "InstLine" : 8,
+        "InstName" : "ha1",
+        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
+        "ModuleLine" : 1,
+        "ModuleName" : "halfadder"
+       },
+       {
+        "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
+        "InstLine" : 9,
+        "InstName" : "ha2",
+        "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
+        "ModuleLine" : 1,
+        "ModuleName" : "halfadder"
+       }
+      ]
+     }
+    ]
+   }
+  ]
+ }
 ]
--- a/gowin/fpga_project/impl/temp/rtl_parser_arg.json
+++ b/gowin/fpga_project/impl/temp/rtl_parser_arg.json
@@ -1,29 +1,29 @@
-{
- "Device" : "GW2A-18C",
- "Files" : [
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
-   "Type" : "verilog"
-  },
-  {
-   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
-   "Type" : "verilog"
-  }
- ],
- "IncludePath" : [
-
- ],
- "LoopLimit" : 2000,
- "ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/impl/temp/rtl_parser.result",
- "Top" : "",
- "VerilogStd" : "verilog_2001",
- "VhdlStd" : "vhdl_93"
+{
+ "Device" : "GW2A-18C",
+ "Files" : [
+  {
+   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
+   "Type" : "verilog"
+  },
+  {
+   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
+   "Type" : "verilog"
+  },
+  {
+   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
+   "Type" : "verilog"
+  },
+  {
+   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
+   "Type" : "verilog"
+  }
+ ],
+ "IncludePath" : [
+
+ ],
+ "LoopLimit" : 2000,
+ "ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/impl/temp/rtl_parser.result",
+ "Top" : "",
+ "VerilogStd" : "verilog_2001",
+ "VhdlStd" : "vhdl_93"
 }