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rearrangement

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k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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76
gowin/fpga_project/impl/gwsynthesis/fpga_project.log
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@ -1,38 +1,38 @@
GowinSynthesis start
Running parser ...
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v'
Compiling module 'ledTest'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v":1)
Compiling module 'bit3adder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":1)
Compiling module 'halfadder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v":1)
Compiling module 'fulladder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":1)
NOTE (EX0101) : Current top module is "ledTest"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "bit3adder" instantiated to "adder" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v":12)
WARN (NL0002) : The module "fulladder" instantiated to "fa0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":10)
WARN (NL0002) : The module "halfadder" instantiated to "ha1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "ha2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "fa1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "ha1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "ha2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":9)
WARN (NL0002) : The module "halfadder" instantiated to "ha0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":9)
[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg" completed
[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project_syn.rpt.html" completed
GowinSynthesis finish
GowinSynthesis start
Running parser ...
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v'
Compiling module 'ledTest'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v":1)
Compiling module 'bit3adder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":1)
Compiling module 'halfadder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v":1)
Compiling module 'fulladder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":1)
NOTE (EX0101) : Current top module is "ledTest"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "bit3adder" instantiated to "adder" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v":12)
WARN (NL0002) : The module "fulladder" instantiated to "fa0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":10)
WARN (NL0002) : The module "halfadder" instantiated to "ha1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "ha2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "fa1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "ha1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "ha2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":9)
WARN (NL0002) : The module "halfadder" instantiated to "ha0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":9)
[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg" completed
[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project_syn.rpt.html" completed
GowinSynthesis finish