kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

rearrangement

Browse Source
This commit is contained in:
k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
gowin/fpga_project/fpga_project.gprj
View File

@ -1,14 +1,14 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/bit3adder.v" type="file.verilog" enable="1"/>
<File path="src/fulladder.v" type="file.verilog" enable="1"/>
<File path="src/halfadder.v" type="file.verilog" enable="1"/>
<File path="src/ledTest.v" type="file.verilog" enable="1"/>
<File path="src/fpga_project.cst" type="file.cst" enable="1"/>
</FileList>
</Project>
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/bit3adder.v" type="file.verilog" enable="1"/>
<File path="src/fulladder.v" type="file.verilog" enable="1"/>
<File path="src/halfadder.v" type="file.verilog" enable="1"/>
<File path="src/ledTest.v" type="file.verilog" enable="1"/>
<File path="src/fpga_project.cst" type="file.cst" enable="1"/>
</FileList>
</Project>