rearrangement
This commit is contained in:
		| @@ -1,218 +1,218 @@ | ||||
| #! /usr/bin/vvp | ||||
| :ivl_version "11.0 (stable)"; | ||||
| :ivl_delay_selection "TYPICAL"; | ||||
| :vpi_time_precision + 0; | ||||
| :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; | ||||
| :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; | ||||
| :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; | ||||
| :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; | ||||
| :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; | ||||
| S_0x55f4b1a88210 .scope module, "bit3Tb" "bit3Tb" 2 1; | ||||
|  .timescale 0 0; | ||||
| v0x55f4b1aba170_0 .var "r1", 2 0; | ||||
| v0x55f4b1aba230_0 .var "r2", 2 0; | ||||
| v0x55f4b1aba300_0 .net "w1", 3 0, L_0x55f4b1abb700;  1 drivers | ||||
| S_0x55f4b1a81ef0 .scope module, "uut" "bit3adder" 2 6, 3 1 0, S_0x55f4b1a88210; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 3 "A"; | ||||
|     .port_info 1 /INPUT 3 "B"; | ||||
|     .port_info 2 /OUTPUT 4 "C"; | ||||
| v0x55f4b1ab9cc0_0 .net "A", 2 0, v0x55f4b1aba170_0;  1 drivers | ||||
| v0x55f4b1ab9dc0_0 .net "B", 2 0, v0x55f4b1aba230_0;  1 drivers | ||||
| v0x55f4b1ab9ea0_0 .net "C", 3 0, L_0x55f4b1abb700;  alias, 1 drivers | ||||
| v0x55f4b1ab9f60_0 .net "c1", 0 0, L_0x55f4b1aba500;  1 drivers | ||||
| v0x55f4b1aba000_0 .net "c2", 0 0, L_0x55f4b1ababd0;  1 drivers | ||||
| L_0x55f4b1aba5c0 .part v0x55f4b1aba170_0, 0, 1; | ||||
| L_0x55f4b1aba6b0 .part v0x55f4b1aba230_0, 0, 1; | ||||
| L_0x55f4b1abad10 .part v0x55f4b1aba170_0, 1, 1; | ||||
| L_0x55f4b1abae40 .part v0x55f4b1aba230_0, 1, 1; | ||||
| L_0x55f4b1abb340 .part v0x55f4b1aba170_0, 2, 1; | ||||
| L_0x55f4b1abb500 .part v0x55f4b1aba230_0, 2, 1; | ||||
| L_0x55f4b1abb700 .concat8 [ 1 1 1 1], L_0x55f4b1aba400, L_0x55f4b1aba9b0, L_0x55f4b1abb090, L_0x55f4b1abb2b0; | ||||
| S_0x55f4b1a81d10 .scope module, "fa0" "fulladder" 3 10, 4 1 0, S_0x55f4b1a81ef0; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /INPUT 1 "C0"; | ||||
|     .port_info 3 /OUTPUT 1 "S"; | ||||
|     .port_info 4 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1ababd0 .functor OR 1, L_0x55f4b1abab40, L_0x55f4b1aba8d0, C4<0>, C4<0>; | ||||
| v0x55f4b1ab7ae0_0 .net "A", 0 0, L_0x55f4b1abad10;  1 drivers | ||||
| v0x55f4b1ab7ba0_0 .net "B", 0 0, L_0x55f4b1abae40;  1 drivers | ||||
| v0x55f4b1ab7c70_0 .net "C", 0 0, L_0x55f4b1ababd0;  alias, 1 drivers | ||||
| v0x55f4b1ab7d40_0 .net "C0", 0 0, L_0x55f4b1aba500;  alias, 1 drivers | ||||
| v0x55f4b1ab7e10_0 .net "C1", 0 0, L_0x55f4b1aba8d0;  1 drivers | ||||
| v0x55f4b1ab7f00_0 .net "C2", 0 0, L_0x55f4b1abab40;  1 drivers | ||||
| v0x55f4b1ab7fd0_0 .net "S", 0 0, L_0x55f4b1aba9b0;  1 drivers | ||||
| v0x55f4b1ab80a0_0 .net "S1", 0 0, L_0x55f4b1aba7a0;  1 drivers | ||||
| S_0x55f4b1a98e60 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1a81d10; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /OUTPUT 1 "S"; | ||||
|     .port_info 3 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1aba7a0 .functor XOR 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<0>, C4<0>; | ||||
| L_0x55f4b1aba8d0 .functor AND 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<1>, C4<1>; | ||||
| v0x55f4b1a89ba0_0 .net "A", 0 0, L_0x55f4b1abad10;  alias, 1 drivers | ||||
| v0x55f4b1a89950_0 .net "B", 0 0, L_0x55f4b1abae40;  alias, 1 drivers | ||||
| v0x55f4b1a885d0_0 .net "C", 0 0, L_0x55f4b1aba8d0;  alias, 1 drivers | ||||
| v0x55f4b1a87200_0 .net "S", 0 0, L_0x55f4b1aba7a0;  alias, 1 drivers | ||||
| S_0x55f4b1ab74f0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1a81d10; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /OUTPUT 1 "S"; | ||||
|     .port_info 3 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1aba9b0 .functor XOR 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<0>, C4<0>; | ||||
| L_0x55f4b1abab40 .functor AND 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<1>, C4<1>; | ||||
| v0x55f4b1ab7760_0 .net "A", 0 0, L_0x55f4b1aba7a0;  alias, 1 drivers | ||||
| v0x55f4b1ab7800_0 .net "B", 0 0, L_0x55f4b1aba500;  alias, 1 drivers | ||||
| v0x55f4b1ab78a0_0 .net "C", 0 0, L_0x55f4b1abab40;  alias, 1 drivers | ||||
| v0x55f4b1ab7970_0 .net "S", 0 0, L_0x55f4b1aba9b0;  alias, 1 drivers | ||||
| S_0x55f4b1ab8190 .scope module, "fa1" "fulladder" 3 11, 4 1 0, S_0x55f4b1a81ef0; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /INPUT 1 "C0"; | ||||
|     .port_info 3 /OUTPUT 1 "S"; | ||||
|     .port_info 4 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1abb2b0 .functor OR 1, L_0x55f4b1abb220, L_0x55f4b1abb000, C4<0>, C4<0>; | ||||
| v0x55f4b1ab8fe0_0 .net "A", 0 0, L_0x55f4b1abb340;  1 drivers | ||||
| v0x55f4b1ab90a0_0 .net "B", 0 0, L_0x55f4b1abb500;  1 drivers | ||||
| v0x55f4b1ab9170_0 .net "C", 0 0, L_0x55f4b1abb2b0;  1 drivers | ||||
| v0x55f4b1ab9240_0 .net "C0", 0 0, L_0x55f4b1ababd0;  alias, 1 drivers | ||||
| v0x55f4b1ab9330_0 .net "C1", 0 0, L_0x55f4b1abb000;  1 drivers | ||||
| v0x55f4b1ab9420_0 .net "C2", 0 0, L_0x55f4b1abb220;  1 drivers | ||||
| v0x55f4b1ab94c0_0 .net "S", 0 0, L_0x55f4b1abb090;  1 drivers | ||||
| v0x55f4b1ab9590_0 .net "S1", 0 0, L_0x55f4b1abaf70;  1 drivers | ||||
| S_0x55f4b1ab8370 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1ab8190; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /OUTPUT 1 "S"; | ||||
|     .port_info 3 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1abaf70 .functor XOR 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<0>, C4<0>; | ||||
| L_0x55f4b1abb000 .functor AND 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<1>, C4<1>; | ||||
| v0x55f4b1ab85f0_0 .net "A", 0 0, L_0x55f4b1abb340;  alias, 1 drivers | ||||
| v0x55f4b1ab86d0_0 .net "B", 0 0, L_0x55f4b1abb500;  alias, 1 drivers | ||||
| v0x55f4b1ab8790_0 .net "C", 0 0, L_0x55f4b1abb000;  alias, 1 drivers | ||||
| v0x55f4b1ab8860_0 .net "S", 0 0, L_0x55f4b1abaf70;  alias, 1 drivers | ||||
| S_0x55f4b1ab89d0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1ab8190; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /OUTPUT 1 "S"; | ||||
|     .port_info 3 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1abb090 .functor XOR 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<0>, C4<0>; | ||||
| L_0x55f4b1abb220 .functor AND 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<1>, C4<1>; | ||||
| v0x55f4b1ab8c40_0 .net "A", 0 0, L_0x55f4b1abaf70;  alias, 1 drivers | ||||
| v0x55f4b1ab8d10_0 .net "B", 0 0, L_0x55f4b1ababd0;  alias, 1 drivers | ||||
| v0x55f4b1ab8de0_0 .net "C", 0 0, L_0x55f4b1abb220;  alias, 1 drivers | ||||
| v0x55f4b1ab8eb0_0 .net "S", 0 0, L_0x55f4b1abb090;  alias, 1 drivers | ||||
| S_0x55f4b1ab9680 .scope module, "ha0" "halfadder" 3 9, 5 1 0, S_0x55f4b1a81ef0; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /OUTPUT 1 "S"; | ||||
|     .port_info 3 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1aba400 .functor XOR 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<0>, C4<0>; | ||||
| L_0x55f4b1aba500 .functor AND 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<1>, C4<1>; | ||||
| v0x55f4b1ab9900_0 .net "A", 0 0, L_0x55f4b1aba5c0;  1 drivers | ||||
| v0x55f4b1ab99c0_0 .net "B", 0 0, L_0x55f4b1aba6b0;  1 drivers | ||||
| v0x55f4b1ab9a80_0 .net "C", 0 0, L_0x55f4b1aba500;  alias, 1 drivers | ||||
| v0x55f4b1ab9ba0_0 .net "S", 0 0, L_0x55f4b1aba400;  1 drivers | ||||
|     .scope S_0x55f4b1a88210; | ||||
| T_0 ; | ||||
|     %vpi_call 2 13 "$dumpfile", "bit3.vcd" {0 0 0}; | ||||
|     %vpi_call 2 14 "$dumpvars" {0 0 0}; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 7, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 1, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 6, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 2, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 5, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 3, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 4, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 4, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 3, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 5, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 2, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 6, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 1, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 7, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 1, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 2, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 3, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 4, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 5, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 6, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 7, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %vpi_call 2 33 "$display", "Done" {0 0 0}; | ||||
|     %end; | ||||
|     .thread T_0; | ||||
| # The file index is used to find the file name in the following table. | ||||
| :file_names 6; | ||||
|     "N/A"; | ||||
|     "<interactive>"; | ||||
|     "bit3Tb.v"; | ||||
|     "bit3adder.v"; | ||||
|     "fulladder.v"; | ||||
|     "halfadder.v"; | ||||
| #! /usr/bin/vvp | ||||
| :ivl_version "11.0 (stable)"; | ||||
| :ivl_delay_selection "TYPICAL"; | ||||
| :vpi_time_precision + 0; | ||||
| :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; | ||||
| :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; | ||||
| :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; | ||||
| :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; | ||||
| :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; | ||||
| S_0x55f4b1a88210 .scope module, "bit3Tb" "bit3Tb" 2 1; | ||||
|  .timescale 0 0; | ||||
| v0x55f4b1aba170_0 .var "r1", 2 0; | ||||
| v0x55f4b1aba230_0 .var "r2", 2 0; | ||||
| v0x55f4b1aba300_0 .net "w1", 3 0, L_0x55f4b1abb700;  1 drivers | ||||
| S_0x55f4b1a81ef0 .scope module, "uut" "bit3adder" 2 6, 3 1 0, S_0x55f4b1a88210; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 3 "A"; | ||||
|     .port_info 1 /INPUT 3 "B"; | ||||
|     .port_info 2 /OUTPUT 4 "C"; | ||||
| v0x55f4b1ab9cc0_0 .net "A", 2 0, v0x55f4b1aba170_0;  1 drivers | ||||
| v0x55f4b1ab9dc0_0 .net "B", 2 0, v0x55f4b1aba230_0;  1 drivers | ||||
| v0x55f4b1ab9ea0_0 .net "C", 3 0, L_0x55f4b1abb700;  alias, 1 drivers | ||||
| v0x55f4b1ab9f60_0 .net "c1", 0 0, L_0x55f4b1aba500;  1 drivers | ||||
| v0x55f4b1aba000_0 .net "c2", 0 0, L_0x55f4b1ababd0;  1 drivers | ||||
| L_0x55f4b1aba5c0 .part v0x55f4b1aba170_0, 0, 1; | ||||
| L_0x55f4b1aba6b0 .part v0x55f4b1aba230_0, 0, 1; | ||||
| L_0x55f4b1abad10 .part v0x55f4b1aba170_0, 1, 1; | ||||
| L_0x55f4b1abae40 .part v0x55f4b1aba230_0, 1, 1; | ||||
| L_0x55f4b1abb340 .part v0x55f4b1aba170_0, 2, 1; | ||||
| L_0x55f4b1abb500 .part v0x55f4b1aba230_0, 2, 1; | ||||
| L_0x55f4b1abb700 .concat8 [ 1 1 1 1], L_0x55f4b1aba400, L_0x55f4b1aba9b0, L_0x55f4b1abb090, L_0x55f4b1abb2b0; | ||||
| S_0x55f4b1a81d10 .scope module, "fa0" "fulladder" 3 10, 4 1 0, S_0x55f4b1a81ef0; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /INPUT 1 "C0"; | ||||
|     .port_info 3 /OUTPUT 1 "S"; | ||||
|     .port_info 4 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1ababd0 .functor OR 1, L_0x55f4b1abab40, L_0x55f4b1aba8d0, C4<0>, C4<0>; | ||||
| v0x55f4b1ab7ae0_0 .net "A", 0 0, L_0x55f4b1abad10;  1 drivers | ||||
| v0x55f4b1ab7ba0_0 .net "B", 0 0, L_0x55f4b1abae40;  1 drivers | ||||
| v0x55f4b1ab7c70_0 .net "C", 0 0, L_0x55f4b1ababd0;  alias, 1 drivers | ||||
| v0x55f4b1ab7d40_0 .net "C0", 0 0, L_0x55f4b1aba500;  alias, 1 drivers | ||||
| v0x55f4b1ab7e10_0 .net "C1", 0 0, L_0x55f4b1aba8d0;  1 drivers | ||||
| v0x55f4b1ab7f00_0 .net "C2", 0 0, L_0x55f4b1abab40;  1 drivers | ||||
| v0x55f4b1ab7fd0_0 .net "S", 0 0, L_0x55f4b1aba9b0;  1 drivers | ||||
| v0x55f4b1ab80a0_0 .net "S1", 0 0, L_0x55f4b1aba7a0;  1 drivers | ||||
| S_0x55f4b1a98e60 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1a81d10; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /OUTPUT 1 "S"; | ||||
|     .port_info 3 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1aba7a0 .functor XOR 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<0>, C4<0>; | ||||
| L_0x55f4b1aba8d0 .functor AND 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<1>, C4<1>; | ||||
| v0x55f4b1a89ba0_0 .net "A", 0 0, L_0x55f4b1abad10;  alias, 1 drivers | ||||
| v0x55f4b1a89950_0 .net "B", 0 0, L_0x55f4b1abae40;  alias, 1 drivers | ||||
| v0x55f4b1a885d0_0 .net "C", 0 0, L_0x55f4b1aba8d0;  alias, 1 drivers | ||||
| v0x55f4b1a87200_0 .net "S", 0 0, L_0x55f4b1aba7a0;  alias, 1 drivers | ||||
| S_0x55f4b1ab74f0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1a81d10; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /OUTPUT 1 "S"; | ||||
|     .port_info 3 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1aba9b0 .functor XOR 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<0>, C4<0>; | ||||
| L_0x55f4b1abab40 .functor AND 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<1>, C4<1>; | ||||
| v0x55f4b1ab7760_0 .net "A", 0 0, L_0x55f4b1aba7a0;  alias, 1 drivers | ||||
| v0x55f4b1ab7800_0 .net "B", 0 0, L_0x55f4b1aba500;  alias, 1 drivers | ||||
| v0x55f4b1ab78a0_0 .net "C", 0 0, L_0x55f4b1abab40;  alias, 1 drivers | ||||
| v0x55f4b1ab7970_0 .net "S", 0 0, L_0x55f4b1aba9b0;  alias, 1 drivers | ||||
| S_0x55f4b1ab8190 .scope module, "fa1" "fulladder" 3 11, 4 1 0, S_0x55f4b1a81ef0; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /INPUT 1 "C0"; | ||||
|     .port_info 3 /OUTPUT 1 "S"; | ||||
|     .port_info 4 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1abb2b0 .functor OR 1, L_0x55f4b1abb220, L_0x55f4b1abb000, C4<0>, C4<0>; | ||||
| v0x55f4b1ab8fe0_0 .net "A", 0 0, L_0x55f4b1abb340;  1 drivers | ||||
| v0x55f4b1ab90a0_0 .net "B", 0 0, L_0x55f4b1abb500;  1 drivers | ||||
| v0x55f4b1ab9170_0 .net "C", 0 0, L_0x55f4b1abb2b0;  1 drivers | ||||
| v0x55f4b1ab9240_0 .net "C0", 0 0, L_0x55f4b1ababd0;  alias, 1 drivers | ||||
| v0x55f4b1ab9330_0 .net "C1", 0 0, L_0x55f4b1abb000;  1 drivers | ||||
| v0x55f4b1ab9420_0 .net "C2", 0 0, L_0x55f4b1abb220;  1 drivers | ||||
| v0x55f4b1ab94c0_0 .net "S", 0 0, L_0x55f4b1abb090;  1 drivers | ||||
| v0x55f4b1ab9590_0 .net "S1", 0 0, L_0x55f4b1abaf70;  1 drivers | ||||
| S_0x55f4b1ab8370 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1ab8190; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /OUTPUT 1 "S"; | ||||
|     .port_info 3 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1abaf70 .functor XOR 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<0>, C4<0>; | ||||
| L_0x55f4b1abb000 .functor AND 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<1>, C4<1>; | ||||
| v0x55f4b1ab85f0_0 .net "A", 0 0, L_0x55f4b1abb340;  alias, 1 drivers | ||||
| v0x55f4b1ab86d0_0 .net "B", 0 0, L_0x55f4b1abb500;  alias, 1 drivers | ||||
| v0x55f4b1ab8790_0 .net "C", 0 0, L_0x55f4b1abb000;  alias, 1 drivers | ||||
| v0x55f4b1ab8860_0 .net "S", 0 0, L_0x55f4b1abaf70;  alias, 1 drivers | ||||
| S_0x55f4b1ab89d0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1ab8190; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /OUTPUT 1 "S"; | ||||
|     .port_info 3 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1abb090 .functor XOR 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<0>, C4<0>; | ||||
| L_0x55f4b1abb220 .functor AND 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<1>, C4<1>; | ||||
| v0x55f4b1ab8c40_0 .net "A", 0 0, L_0x55f4b1abaf70;  alias, 1 drivers | ||||
| v0x55f4b1ab8d10_0 .net "B", 0 0, L_0x55f4b1ababd0;  alias, 1 drivers | ||||
| v0x55f4b1ab8de0_0 .net "C", 0 0, L_0x55f4b1abb220;  alias, 1 drivers | ||||
| v0x55f4b1ab8eb0_0 .net "S", 0 0, L_0x55f4b1abb090;  alias, 1 drivers | ||||
| S_0x55f4b1ab9680 .scope module, "ha0" "halfadder" 3 9, 5 1 0, S_0x55f4b1a81ef0; | ||||
|  .timescale 0 0; | ||||
|     .port_info 0 /INPUT 1 "A"; | ||||
|     .port_info 1 /INPUT 1 "B"; | ||||
|     .port_info 2 /OUTPUT 1 "S"; | ||||
|     .port_info 3 /OUTPUT 1 "C"; | ||||
| L_0x55f4b1aba400 .functor XOR 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<0>, C4<0>; | ||||
| L_0x55f4b1aba500 .functor AND 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<1>, C4<1>; | ||||
| v0x55f4b1ab9900_0 .net "A", 0 0, L_0x55f4b1aba5c0;  1 drivers | ||||
| v0x55f4b1ab99c0_0 .net "B", 0 0, L_0x55f4b1aba6b0;  1 drivers | ||||
| v0x55f4b1ab9a80_0 .net "C", 0 0, L_0x55f4b1aba500;  alias, 1 drivers | ||||
| v0x55f4b1ab9ba0_0 .net "S", 0 0, L_0x55f4b1aba400;  1 drivers | ||||
|     .scope S_0x55f4b1a88210; | ||||
| T_0 ; | ||||
|     %vpi_call 2 13 "$dumpfile", "bit3.vcd" {0 0 0}; | ||||
|     %vpi_call 2 14 "$dumpvars" {0 0 0}; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 7, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 1, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 6, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 2, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 5, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 3, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 4, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 4, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 3, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 5, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 2, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 6, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 1, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 7, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 1, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 2, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 3, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 4, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 5, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 6, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %pushi/vec4 7, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba170_0, 0, 3; | ||||
|     %pushi/vec4 0, 0, 3; | ||||
|     %store/vec4 v0x55f4b1aba230_0, 0, 3; | ||||
|     %delay 10, 0; | ||||
|     %vpi_call 2 33 "$display", "Done" {0 0 0}; | ||||
|     %end; | ||||
|     .thread T_0; | ||||
| # The file index is used to find the file name in the following table. | ||||
| :file_names 6; | ||||
|     "N/A"; | ||||
|     "<interactive>"; | ||||
|     "bit3Tb.v"; | ||||
|     "bit3adder.v"; | ||||
|     "fulladder.v"; | ||||
|     "halfadder.v"; | ||||
|   | ||||
		Reference in New Issue
	
	Block a user