From a1339a24a0334d329bcaaf4f64c8ba68751b4422 Mon Sep 17 00:00:00 2001 From: k0rrluna Date: Mon, 2 Dec 2024 22:35:19 +0300 Subject: [PATCH] verible --- {bin => verible/bin}/.Formatter.swp | Bin {bin => verible/bin}/.Here’s.swp | Bin {bin => verible/bin}/.Verible.swp | Bin {bin => verible/bin}/.Verilog.swp | Bin {bin => verible/bin}/.a.swp | Bin {bin => verible/bin}/.align.swp | Bin {bin => verible/bin}/.configuration.swp | Bin {bin => verible/bin}/.file.swp | Bin {bin => verible/bin}/.for.swp | Bin {bin => verible/bin}/.from.swp | Bin {bin => verible/bin}/.project,.swp | Bin {bin => verible/bin}/.tailored.swp | Bin {bin => verible/bin}/.the.swp | Bin {bin => verible/bin}/.to.swp | Bin .../bin}/.verible-verilog-format.properties | 0 {bin => verible/bin}/.with.swp | Bin {bin => verible/bin}/verible-verilog-diff | Bin {bin => verible/bin}/verible-verilog-format | Bin .../bin}/verible-verilog-kythe-extractor | Bin {bin => verible/bin}/verible-verilog-lint | Bin {bin => verible/bin}/verible-verilog-ls | Bin {bin => verible/bin}/verible-verilog-obfuscate | Bin {bin => verible/bin}/verible-verilog-preprocessor | Bin {bin => verible/bin}/verible-verilog-project | Bin {bin => verible/bin}/verible-verilog-syntax | Bin 25 files changed, 0 insertions(+), 0 deletions(-) rename {bin => verible/bin}/.Formatter.swp (100%) rename {bin => verible/bin}/.Here’s.swp (100%) rename {bin => verible/bin}/.Verible.swp (100%) rename {bin => verible/bin}/.Verilog.swp (100%) rename {bin => verible/bin}/.a.swp (100%) rename {bin => verible/bin}/.align.swp (100%) rename {bin => verible/bin}/.configuration.swp (100%) rename {bin => verible/bin}/.file.swp (100%) rename {bin => verible/bin}/.for.swp (100%) rename {bin => verible/bin}/.from.swp (100%) rename {bin => verible/bin}/.project,.swp (100%) rename {bin => verible/bin}/.tailored.swp (100%) rename {bin => verible/bin}/.the.swp (100%) rename {bin => verible/bin}/.to.swp (100%) rename {bin => verible/bin}/.verible-verilog-format.properties (100%) rename {bin => verible/bin}/.with.swp (100%) rename {bin => verible/bin}/verible-verilog-diff (100%) mode change 100755 => 100644 rename {bin => verible/bin}/verible-verilog-format (100%) mode change 100755 => 100644 rename {bin => verible/bin}/verible-verilog-kythe-extractor (100%) mode change 100755 => 100644 rename {bin => verible/bin}/verible-verilog-lint (100%) mode change 100755 => 100644 rename {bin => verible/bin}/verible-verilog-ls (100%) mode change 100755 => 100644 rename {bin => verible/bin}/verible-verilog-obfuscate (100%) mode change 100755 => 100644 rename {bin => verible/bin}/verible-verilog-preprocessor (100%) mode change 100755 => 100644 rename {bin => verible/bin}/verible-verilog-project (100%) mode change 100755 => 100644 rename {bin => verible/bin}/verible-verilog-syntax (100%) mode change 100755 => 100644 diff --git a/bin/.Formatter.swp b/verible/bin/.Formatter.swp similarity index 100% rename from bin/.Formatter.swp rename to verible/bin/.Formatter.swp diff --git a/bin/.Here’s.swp b/verible/bin/.Here’s.swp similarity index 100% rename from bin/.Here’s.swp rename to verible/bin/.Here’s.swp diff --git a/bin/.Verible.swp b/verible/bin/.Verible.swp similarity index 100% rename from bin/.Verible.swp rename to verible/bin/.Verible.swp diff --git a/bin/.Verilog.swp b/verible/bin/.Verilog.swp similarity index 100% rename from bin/.Verilog.swp rename to verible/bin/.Verilog.swp diff --git a/bin/.a.swp b/verible/bin/.a.swp similarity index 100% rename from bin/.a.swp rename to verible/bin/.a.swp diff --git a/bin/.align.swp b/verible/bin/.align.swp similarity index 100% rename from bin/.align.swp rename to verible/bin/.align.swp diff --git a/bin/.configuration.swp b/verible/bin/.configuration.swp similarity index 100% rename from bin/.configuration.swp rename to verible/bin/.configuration.swp diff --git a/bin/.file.swp b/verible/bin/.file.swp similarity index 100% rename from bin/.file.swp rename to verible/bin/.file.swp diff --git a/bin/.for.swp b/verible/bin/.for.swp similarity index 100% rename from bin/.for.swp rename to verible/bin/.for.swp diff --git a/bin/.from.swp b/verible/bin/.from.swp similarity index 100% rename from bin/.from.swp rename to verible/bin/.from.swp diff --git a/bin/.project,.swp b/verible/bin/.project,.swp similarity index 100% rename from bin/.project,.swp rename to verible/bin/.project,.swp diff --git a/bin/.tailored.swp b/verible/bin/.tailored.swp similarity index 100% rename from bin/.tailored.swp rename to verible/bin/.tailored.swp diff --git a/bin/.the.swp b/verible/bin/.the.swp similarity index 100% rename from bin/.the.swp rename to verible/bin/.the.swp diff --git a/bin/.to.swp b/verible/bin/.to.swp similarity index 100% rename from bin/.to.swp rename to verible/bin/.to.swp diff --git a/bin/.verible-verilog-format.properties b/verible/bin/.verible-verilog-format.properties similarity index 100% rename from bin/.verible-verilog-format.properties rename to verible/bin/.verible-verilog-format.properties diff --git a/bin/.with.swp b/verible/bin/.with.swp similarity index 100% rename from bin/.with.swp rename to verible/bin/.with.swp diff --git a/bin/verible-verilog-diff b/verible/bin/verible-verilog-diff old mode 100755 new mode 100644 similarity index 100% rename from bin/verible-verilog-diff rename to verible/bin/verible-verilog-diff diff --git a/bin/verible-verilog-format b/verible/bin/verible-verilog-format old mode 100755 new mode 100644 similarity index 100% rename from bin/verible-verilog-format rename to verible/bin/verible-verilog-format diff --git a/bin/verible-verilog-kythe-extractor b/verible/bin/verible-verilog-kythe-extractor old mode 100755 new mode 100644 similarity index 100% rename from bin/verible-verilog-kythe-extractor rename to verible/bin/verible-verilog-kythe-extractor diff --git a/bin/verible-verilog-lint b/verible/bin/verible-verilog-lint old mode 100755 new mode 100644 similarity index 100% rename from bin/verible-verilog-lint rename to verible/bin/verible-verilog-lint diff --git a/bin/verible-verilog-ls b/verible/bin/verible-verilog-ls old mode 100755 new mode 100644 similarity index 100% rename from bin/verible-verilog-ls rename to verible/bin/verible-verilog-ls diff --git a/bin/verible-verilog-obfuscate b/verible/bin/verible-verilog-obfuscate old mode 100755 new mode 100644 similarity index 100% rename from bin/verible-verilog-obfuscate rename to verible/bin/verible-verilog-obfuscate diff --git a/bin/verible-verilog-preprocessor b/verible/bin/verible-verilog-preprocessor old mode 100755 new mode 100644 similarity index 100% rename from bin/verible-verilog-preprocessor rename to verible/bin/verible-verilog-preprocessor diff --git a/bin/verible-verilog-project b/verible/bin/verible-verilog-project old mode 100755 new mode 100644 similarity index 100% rename from bin/verible-verilog-project rename to verible/bin/verible-verilog-project diff --git a/bin/verible-verilog-syntax b/verible/bin/verible-verilog-syntax old mode 100755 new mode 100644 similarity index 100% rename from bin/verible-verilog-syntax rename to verible/bin/verible-verilog-syntax