73 lines
1.3 KiB
Verilog
73 lines
1.3 KiB
Verilog
/*
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* testbench for femtosoc/femtorv32
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*
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* 1. select one of the processors by uncommenting one of the
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* lines NRV_FEMTORV32_XXX
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*
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* 2. edit FIRMWARE/config.mk and make sure ARCH corresponds to
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* selected processor.
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*
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* $ cd FIRMWARE/EXAMPLES
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* $ make hello.hex
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* $ cd ../..
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* $ make testbench
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*
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* Uncomment VERBOSE for extensive information (states ...)
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*/
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`timescale 1ns/1ns
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//`include "femtosoc_config.v"
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//
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//`ifndef BENCH
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//`define BENCH
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//`endif
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`define VERBOSE // Uncomment to have detailed log traces of all states
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`include "femtosoc.v"
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`ifdef VERILATOR
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module femtoRV32_bench(
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input pclk,
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output oled_DIN, oled_CLK, oled_CS, oled_DC, oled_RST
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);
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`else
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module femtoRV32_bench();
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reg pclk;
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`endif
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wire [4:0] LEDs;
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wire TXD;
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femtosoc uut(
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.pclk(pclk),
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.TXD(TXD),
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.RXD(1'b0),
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.RESET(1'b0),
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`ifdef NRV_IO_SSD1351_1331
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.oled_DIN(oled_DIN),
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.oled_CLK(oled_CLK),
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.oled_CS(oled_CS),
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.oled_DC(oled_DC),
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.oled_RST(oled_RST),
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`endif
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.D1(LEDs[0]),
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.D2(LEDs[1]),
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.D3(LEDs[2]),
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.D4(LEDs[3]),
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.D5(LEDs[4])
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);
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`ifndef VERILATOR
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initial begin
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pclk = 0;
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forever begin
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#1 pclk = ~pclk;
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end
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end
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`endif
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endmodule
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