155 lines
5.0 KiB
Verilog
155 lines
5.0 KiB
Verilog
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// Define one of:
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// MODE_640x480, MODE_800x600, MODE_1024x768, MODE_1280x1024.
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// ("physical mode" sent to the HDMI)
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`include "TMDS_encoder.v"
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// Generate HDMI signal from VGA signal
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module GFX_hdmi(
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input wire pixel_clk, // pixel clock
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input wire pixel_clk_x5, // 5 times pixel clock freq (used by TMDS serializer)
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// The TMDS serializers operate at (pixel_clock_freq * 10),
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// but we use DDR mode, hence (pixel_clock_freq * 5).
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input wire [7:0] R,
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input wire [7:0] G,
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input wire [7:0] B,
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input wire hsync,
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input wire vsync,
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input wire draw_area,
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output wire [3:0] gpdi_dp // HDMI signals, blue, green, red, clock
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// dgpi_dn generated by pins (see, e.g., ulx3s.lpf)
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);
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// RGB TMDS encoding
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// Generate 10-bits TMDS red,green,blue signals. Blue embeds HSync/VSync in its
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// control part.
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wire [9:0] TMDS_R, TMDS_G, TMDS_B;
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TMDS_encoder encode_R(.clk(pixel_clk), .VD(R), .CD(2'b00) , .VDE(draw_area), .TMDS(TMDS_R));
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TMDS_encoder encode_G(.clk(pixel_clk), .VD(G), .CD(2'b00) , .VDE(draw_area), .TMDS(TMDS_G));
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TMDS_encoder encode_B(.clk(pixel_clk), .VD(B), .CD({vsync,hsync}), .VDE(draw_area), .TMDS(TMDS_B));
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// Modulo-5 clock divider.
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reg [4:0] TMDS_mod5=1;
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wire TMDS_shift_load = TMDS_mod5[4];
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always @(posedge pixel_clk_x5) TMDS_mod5 <= {TMDS_mod5[3:0],TMDS_mod5[4]};
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// Shifters
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// Every 5 clocks, we get a fresh R,G,B triplet from the TMDS encoders,
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// else we shift.
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reg [9:0] TMDS_shift_R=0, TMDS_shift_G=0, TMDS_shift_B=0;
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always @(posedge pixel_clk_x5) begin
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TMDS_shift_R <= TMDS_shift_load ? TMDS_R : {2'b00,TMDS_shift_R[9:2]};
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TMDS_shift_G <= TMDS_shift_load ? TMDS_G : {2'b00,TMDS_shift_G[9:2]};
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TMDS_shift_B <= TMDS_shift_load ? TMDS_B : {2'b00,TMDS_shift_B[9:2]};
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end
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// DDR serializers: they send D0 at the rising edge and D1 at the falling edge.
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`ifndef BENCH_OR_LINT
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`ifdef ULX3S
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ODDRX1F ddr_R (.D0(TMDS_shift_R[0]), .D1(TMDS_shift_R[1]), .Q(gpdi_dp[2]), .SCLK(pixel_clk_x5), .RST(1'b0));
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ODDRX1F ddr_G (.D0(TMDS_shift_G[0]), .D1(TMDS_shift_G[1]), .Q(gpdi_dp[1]), .SCLK(pixel_clk_x5), .RST(1'b0));
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ODDRX1F ddr_B (.D0(TMDS_shift_B[0]), .D1(TMDS_shift_B[1]), .Q(gpdi_dp[0]), .SCLK(pixel_clk_x5), .RST(1'b0));
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`endif
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`endif
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// The pixel clock is sent through the fourth differential pair.
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assign gpdi_dp[3] = pixel_clk;
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endmodule
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/**************************************************************************************/
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`ifdef BENCH_OR_LINT
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module GFX_PLL(
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input wire pclk, // the board's clock
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output wire pixel_clk, // pixel clock
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output wire pixel_clk_x5 // 5 times pixel clock freq (used by TMDS serializer)
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);
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assign pixel_clk = pclk;
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assign pixel_clk_x5 = pclk;
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endmodule
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`else
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`ifdef ULX3S
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module GFX_PLL(
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input wire pclk, // the board's clock
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output wire pixel_clk, // pixel clock
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output wire pixel_clk_x5 // 5 times pixel clock freq (used by TMDS serializer)
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// The TMDS serializers operate at (pixel_clock_freq * 10),
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// but we use DDR mode, hence (pixel_clock_freq * 5).
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);
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// The parameters of the PLL,
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// They are found by using: ecppll -i 25 -o <5*pixel_clock> -f foobar.v
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`ifdef MODE_640x480
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localparam CLKI_DIV = 1;
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localparam CLKOP_DIV = 5;
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localparam CLKOP_CPHASE = 2;
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localparam CLKOP_FPHASE = 0;
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localparam CLKFB_DIV = 5;
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`endif
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`ifdef MODE_800x600
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localparam CLKI_DIV = 1;
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localparam CLKOP_DIV = 3;
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localparam CLKOP_CPHASE = 1;
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localparam CLKOP_FPHASE = 0;
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localparam CLKFB_DIV = 8;
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`endif
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`ifdef MODE_1024x768
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localparam CLKI_DIV = 1;
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localparam CLKOP_DIV = 2;
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localparam CLKOP_CPHASE = 1;
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localparam CLKOP_FPHASE = 0;
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localparam CLKFB_DIV = 13;
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`endif
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`ifdef MODE_1280x1024
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localparam CLKI_DIV = 3;
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localparam CLKOP_DIV = 1;
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localparam CLKOP_CPHASE = 0;
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localparam CLKOP_FPHASE = 0;
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localparam CLKFB_DIV = 65;
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`endif
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// The PLL converts a 25 MHz clock into a (pixel_clock_freq * 5) clock
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// The (half) TMDS serializer clock is generated on pin CLKOP.
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// In addition, the pixel clock (at TMDS freq/5) is generated on
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// pin CLKOS (hence CLKOS_DIV = 5*CLKOP_DIV).
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(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
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EHXPLLL #(
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.CLKI_DIV(CLKI_DIV),
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.CLKOP_DIV(CLKOP_DIV),
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.CLKOP_CPHASE(CLKOP_CPHASE),
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.CLKOP_FPHASE(CLKOP_FPHASE),
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.CLKOS_ENABLE("ENABLED"),
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.CLKOS_DIV(5*CLKOP_DIV),
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.CLKOS_CPHASE(CLKOP_CPHASE),
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.CLKOS_FPHASE(CLKOP_FPHASE),
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.CLKFB_DIV(CLKFB_DIV)
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) pll_i (
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.CLKI(pclk),
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.CLKOP(pixel_clk_x5),
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.CLKFB(pixel_clk_x5),
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.CLKOS(pixel_clk),
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.PHASESEL0(1'b0),
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.PHASESEL1(1'b0),
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.PHASEDIR(1'b1),
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.PHASESTEP(1'b1),
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.PHASELOADREG(1'b1),
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.PLLWAKESYNC(1'b0),
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.ENCLKOP(1'b0)
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);
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endmodule
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`endif
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`endif
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