initial

bench_iverilog.v

@@ -0,0 +1,30 @@
+
+module bench();
+   reg CLK;         // Main clock
+   reg RESET;       // Active-low reset
+   wire [4:0] LEDS; // LED outputs
+   reg RXD = 1'b1;  // UART receive (idle high)
+   wire TXD;        // UART transmit
+
+   // Device Under Test
+   SOC uut(
+     .clk(CLK),
+     .rst_i(RESET),
+     .led(LEDS),
+     .RXD(RXD),
+     .TXD(TXD)
+   );
+
+   reg[4:0] prev_LEDS = 0;
+   initial begin
+      CLK = 0;
+      forever begin
+	 #1 CLK = ~CLK;
+	 if(LEDS != prev_LEDS) begin
+	    $display("LEDS = %b",LEDS);
+	 end
+	 prev_LEDS <= LEDS;
+      end
+   end
+endmodule   
+