newStep.v

RTL/DEVICES/uart_picosoc_shrunk.v

@@ -0,0 +1,134 @@
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+ // October 2019, Matthias Koch: Renamed wires and optimizations.
+ // December 2020, Bruno Levy: parameterization with freq and bauds
+ //                            Factorized recv_divcnt and send_divcnt
+ //                            Additional LUT golfing tricks
+
+module buart #(
+  parameter FREQ_MHZ = 12,
+  parameter BAUDS    = 115200
+) (
+    input clk,
+    input resetq,
+
+    output tx,
+    input  rx,
+
+    input  wr,
+    input  rd,
+    input  [7:0] tx_data,
+    output [7:0] rx_data,
+
+    output busy,
+    output valid
+);
+
+   /************** Baud frequency constants ******************/
+
+    parameter divider = FREQ_MHZ * 1000000 / BAUDS;
+    parameter divwidth = $clog2(divider);
+
+    parameter baud_init = divider;
+    parameter half_baud_init = divider/2+1;
+
+   /************* Receiver ***********************************/
+
+    // Trick from Olof Kindgren: use n+1 bit and decrement instead of
+    // incrementing, and test the sign bit.
+
+    reg [divwidth:0] recv_divcnt;
+    wire recv_baud_clk = recv_divcnt[divwidth];
+
+    reg recv_state;
+    reg [8:0] recv_pattern;
+    reg [7:0] recv_buf_data;
+    reg recv_buf_valid;
+
+    assign rx_data = recv_buf_data;
+    assign valid = recv_buf_valid;
+
+
+    always @(posedge clk) begin
+
+       if (rd) recv_buf_valid <= 0;
+ 
+       if (!resetq) recv_buf_valid <= 0;
+
+       case (recv_state)
+
+         0: begin
+               if (!rx) begin
+                 recv_state <= 1;
+		 /* verilator lint_off WIDTH */
+                 recv_divcnt <= half_baud_init;
+		 /* verilator lint_on WIDTH */
+               end
+               recv_pattern <= 0;
+            end
+
+         1: begin
+               if (recv_baud_clk) begin
+
+                 // Inverted start bit shifted through the whole register 
+		 // The idea is to use the start bit as marker 
+		 // for "reception complete", 
+		 // but as initialising registers to 10'b1_11111111_1 
+		 // is more costly than using zero, 
+		 // it is done with inverted logic. 
+                 if (recv_pattern[0]) begin
+                   recv_buf_data  <= ~recv_pattern[8:1];
+                   recv_buf_valid <= 1;
+                   recv_state <= 0;
+                 end else begin
+                   recv_pattern <= {~rx, recv_pattern[8:1]};
+		   /* verilator lint_off WIDTH */		    
+                   recv_divcnt <= baud_init;
+		   /* verilator lint_on WIDTH */
+                 end
+               end else recv_divcnt <= recv_divcnt - 1;
+            end
+
+       endcase
+    end
+
+   /************* Transmitter ******************************/
+
+    reg [divwidth:0] send_divcnt;
+    wire send_baud_clk  = send_divcnt[divwidth];
+
+    reg [9:0] send_pattern = 1;
+    assign tx = send_pattern[0];
+    assign busy = |send_pattern[9:1];
+
+    // The transmitter shifts until the stop bit is on the wire, 
+    // and stops shifting then.
+    always @(posedge clk) begin
+       if (wr) send_pattern <= {1'b1, tx_data[7:0], 1'b0};
+       else if (send_baud_clk & busy) send_pattern <= send_pattern >> 1;
+       /* verilator lint_off WIDTH */		    
+       if (wr | send_baud_clk) send_divcnt <= baud_init;
+                          else send_divcnt <= send_divcnt - 1;
+       /* verilator lint_on WIDTH */		           
+    end
+
+endmodule
+
+