kaltinsoy/learnFPGAProject
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

newStep.v

Browse Source
This commit is contained in:
kaltinsoy
2025-11-27 04:28:54 +03:00
parent a84b8fcfde
commit 6e38a6c1af
85 changed files with 25646 additions and 6801 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
RTL/CONFIGS/arty_config.v Normal file
View File

@@ -0,0 +1,42 @@
// Default femtosoc configuration file for ARTY
/*** Devices ******************************************************************/
`define NRV_IO_LEDS // Mapped IO, LEDs D1,D2,D3,D4 (D5 = errors)
`define NRV_IO_UART // Mapped IO, virtual UART (USB)
`define NRV_IO_SSD1351 // Mapped IO, 128x128x64K OLED screen
//`define NRV_IO_MAX7219 // Mapped IO, 8x8 led matrix
//`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space.
/*** Processor configuration **************************************************/
`define NRV_FREQ 70 // Frequency in MHz, needs to be a multiple of 5
// CORE RV32 subset fmax validated-experimental
//
//`define NRV_FEMTORV32_QUARK // RV32I fmax = 80-110 MHz
//`define NRV_FEMTORV32_TACHYON // RV32I fmax = 100-135 MHz
//`define NRV_FEMTORV32_ELECTRON // RV32IM fmax = 70-80 MHz
//`define NRV_FEMTORV32_INTERMISSUM // RV32IM, IRQ fmax = 60-80 MHz
//`define NRV_FEMTORV32_GRACILIS // RV32IMC, IRQ fmax = 60-80 MHz
`define NRV_FEMTORV32_PETITBATEAU // RV32IMFC, IRQ fmax = 50-80 MHz
//`define NRV_FEMTORV32_TESTDRIVE
`define NRV_RESET_ADDR 0 // The address the processor jumps to on reset
/*** RAM (in bytes, needs to be a multiple of 4)*******************************/
`define NRV_RAM 65536
//`define NRV_RAM 262144 // On the ARTY, does not work with more than 64k,
// I don't know why.
/*** Advanced devices configuration *******************************************/
`define NRV_IO_HARDWARE_CONFIG // Hardware config registers mapped in IO-Space
// (note: firmware libfemtorv32 depends on it)
/******************************************************************************/
`define NRV_NEGATIVE_RESET // reset button active low
`define NRV_CONFIGURED

19
RTL/CONFIGS/bench_config.v Normal file
View File

@@ -0,0 +1,19 @@
`define NRV_IO_LEDS
`define NRV_IO_UART
`define NRV_IO_SSD1351
`define NRV_FREQ 1
//`define NRV_FEMTORV32_QUARK // RV32I (the most elementary femtorv)
//`define NRV_FEMTORV32_ELECTRON // RV32IM
//`define NRV_FEMTORV32_INTERMISSUM // RV32IMzCSR
//`define NRV_FEMTORV32_GRACILIS // RV32IMCzCSR
`define NRV_FEMTORV32_PETITBATEAU // WIP RF32F !!
//`define NRV_FEMTORV32_TESTDRIVE
`define NRV_RESET_ADDR 0
`define NRV_RAM 65536
`define NRV_IO_HARDWARE_CONFIG
`define NRV_CONFIGURED

42
RTL/CONFIGS/cmod_a7_config.v Normal file
View File

@@ -0,0 +1,42 @@
// Default femtosoc configuration file for ARTY
/*** Devices ******************************************************************/
`define NRV_IO_LEDS // Mapped IO, LEDs D1,D2,D3,D4 (D5 = errors)
`define NRV_IO_UART // Mapped IO, virtual UART (USB)
`define NRV_IO_SSD1351 // Mapped IO, 128x128x64K OLED screen
//`define NRV_IO_MAX7219 // Mapped IO, 8x8 led matrix
//`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space.
/*** Processor configuration **************************************************/
`define NRV_FREQ 70 // Frequency in MHz, needs to be a multiple of 5
// CORE RV32 subset fmax validated-experimental
//
//`define NRV_FEMTORV32_QUARK // RV32I fmax = 80-110 MHz
//`define NRV_FEMTORV32_TACHYON // RV32I fmax = 100-135 MHz
//`define NRV_FEMTORV32_ELECTRON // RV32IM fmax = 70-80 MHz
//`define NRV_FEMTORV32_INTERMISSUM // RV32IM, IRQ fmax = 60-80 MHz
//`define NRV_FEMTORV32_GRACILIS // RV32IMC, IRQ fmax = 60-80 MHz
`define NRV_FEMTORV32_PETITBATEAU // RV32IMFC, IRQ fmax = 50-80 MHz
//`define NRV_FEMTORV32_TESTDRIVE
`define NRV_RESET_ADDR 0 // The address the processor jumps to on reset
/*** RAM (in bytes, needs to be a multiple of 4)*******************************/
`define NRV_RAM 65536
//`define NRV_RAM 262144 // On the ARTY, does not work with more than 64k,
// I don't know why.
/*** Advanced devices configuration *******************************************/
`define NRV_IO_HARDWARE_CONFIG // Hardware config registers mapped in IO-Space
// (note: firmware libfemtorv32 depends on it)
/******************************************************************************/
`define NRV_NEGATIVE_RESET // reset button active low
`define NRV_CONFIGURED

36
RTL/CONFIGS/ecp5evn_config.v Normal file
View File

@@ -0,0 +1,36 @@
// Default femtosoc configuration file for IceStick
/************************* Devices **********************************************************************************/
`define NRV_IO_LEDS // Mapped IO, LEDs D1,D2,D3,D4 (D5 is used to display errors)
//`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space. Use with MINIRV32 to run code from SPI flash.
/************************* Frequency ********************************************************************************/
`define NRV_FREQ 65 // Frequency in MHz.
/************************* RAM (in bytes, needs to be a multiple of 4)***********************************************/
`define NRV_RAM 262144 // RAM in bytes
/************************* Processor configuration ******************************************************************/
`define NRV_CSR // Uncomment if using something below (counters,...)
`define NRV_COUNTERS // Uncomment for instr and cycle counters (won't fit on the ICEStick)
`define NRV_COUNTERS_64 // ... and uncomment this one as well if you want 64-bit counters
`define NRV_RV32M // Uncomment for hardware mul and div support (RV32M instructions). Not supported on IceStick !
`define NRV_LATCH_ALU // Uncomment to latch all ALU ops (reduces critical path)
/************************* Advanced processor configuration *********************************************************/
`define NRV_RESET_ADDR 24'h000000
//`define NRV_RESET_ADDR 24'h810000 // Jump execution to SPI Flash (Mapped at 800000h, + leave 64k (10000h) for FPGA bitstream)
`define NRV_IO_HARDWARE_CONFIG // Comment-out to disable hardware config registers mapped in IO-Space
// (only if you use your own firmware, libfemtorv32 depends on it)
/******************************************************************************************************************/
//`define NRV_RUN_FROM_SPI_FLASH // Do not 'readmemh()' firmware from '.hex' file
`define NRV_CONFIGURED

38
RTL/CONFIGS/generic_config.v Normal file
View File

@@ -0,0 +1,38 @@
// Default femtosoc configuration file for IceStick
/************************* Devices **********************************************************************************/
`define NRV_IO_LEDS // Mapped IO, LEDs D1,D2,D3,D4 (D5 is used to display errors)
//`define NRV_IO_UART // Mapped IO, virtual UART (USB)
//`define NRV_IO_SSD1351 // Mapped IO, 128x128x64K OLed screen
//`define NRV_IO_MAX7219 // Mapped IO, 8x8 led matrix
//`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space. Can be used with MINIRV32 to run code from SPI flash.
/************************* Frequency ********************************************************************************/
`define NRV_FREQ 50 // Frequency in MHz. Recomm: 50 MHz (FOMU: 16MHz) Overclocking: 80-100 MHz (HX1K, ECP5)
/************************* RAM (in bytes, needs to be a multiple of 4)***********************************************/
`define NRV_RAM 6144 // default for ICESTICK (cannot do more !)
//`define NRV_RAM 1024 // small ICESTICK config (to further save LUTs if need be)
/************************* Processor configuration ******************************************************************/
//`define NRV_CSR // Uncomment if using something below (counters,...)
//`define NRV_COUNTERS // Uncomment for instr and cycle counters (won't fit on the ICEStick)
//`define NRV_COUNTERS_64 // ... and uncomment this one as well if you want 64-bit counters
`define NRV_TWOSTAGE_SHIFTER // if not RV32M, comment-out if running out of LUTs (at the expense of slower shifts)
//`define NRV_LATCH_ALU // Uncomment to latch all ALU ops (reduces critical path)
/************************* Advanced processor configuration *********************************************************/
`define NRV_RESET_ADDR 0 // The address the processor jumps to on reset
//`define NRV_RESET_ADDR 32'h00800000 // If using NRV_MINIRV32 and mapped SPI Flash, you may want to jump to
// a bootloader or firmware stored there.
`define NRV_IO_HARDWARE_CONFIG // Comment-out to disable hardware config registers mapped in IO-Space
// (only if you use your own firmware, libfemtorv32 depends on it)
/******************************************************************************************************************/

46
RTL/CONFIGS/icebreaker_config.v Normal file
View File

@@ -0,0 +1,46 @@
// Default femtosoc configuration file for IceStick
`define NRV_NEGATIVE_RESET
/************************* Devices **********************************************************************************/
`define NRV_IO_LEDS // Mapped IO, LEDs D1,D2,D3,D4 (D5 is used to display errors)
`define NRV_IO_UART // Mapped IO, virtual UART (USB)
`define NRV_IO_SSD1351 // Mapped IO, 128x128x64K OLed screen
`define NRV_IO_MAX7219 // Mapped IO, 8x8 led matrix
`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space. Can be used with MINIRV32 to run code from SPI flash.
/************************* Processor configuration ******************************************************************/
//`define NRV_FEMTORV32_QUARK_BICYCLE // RV32I
`define NRV_FEMTORV32_ELECTRON // RV32IM
//`define NRV_FEMTORV32_INTERMISSUM // RV32IM + IRQ
//`define NRV_FEMTORV32_GRACILIS // RV32IMC + IRQ
//`define NRV_FEMTORV32_PETITBATEAU // RV32IMFC + IRQ, does not fit on IceBreaker
`define NRV_FREQ 20 // Frequency in MHz. Recomm: 15 MHz Overclocking: 20-25 MHz
`define NRV_RESET_ADDR 32'h00820000 // Jump execution to SPI Flash (800000h, +128k(20000h) for FPGA bitstream)
// tinyraytracer: 30 MHz RV32IM electron 3:12
// 20 MHz RV32IM gracilis 3:44
// 20 MHz RV32IMC gracilis 3:32
// 25 MHz RV32IMC gracilis 2:49
/************************* RAM (in bytes, needs to be a multiple of 4)***********************************************/
// Using the 128 kbytes of single-ported RAM of the ice40-up5k
// Note: cannot initialize it from .hex file, need to run from SPI Flash
`define ICE40UP5K_SPRAM
`define NRV_RAM 131072
// (other option, the 12 kbytes of BRAM, this one can be initialized from .hex file).
//`define NRV_RAM 12288
/************************* Advanced devices configuration *********************************************************/
`define NRV_RUN_FROM_SPI_FLASH // Do not 'readmemh()' firmware from '.hex' file
`define NRV_IO_HARDWARE_CONFIG // Comment-out to disable hardware config registers mapped in IO-Space
// (only if you use your own firmware, libfemtorv32 depends on it)
/******************************************************************************************************************/
`define NRV_CONFIGURED

45
RTL/CONFIGS/icestick_config.v Normal file
View File

@@ -0,0 +1,45 @@
// Default femtosoc configuration file for IceStick
/************************* Devices **********************************************************************************/
`define NRV_IO_LEDS // Mapped IO, LEDs D1,D2,D3,D4 (D5 is used to display errors)
`define NRV_IO_IRDA // In IO_LEDS, support for the IRDA on the IceStick (WIP)
`define NRV_IO_UART // Mapped IO, virtual UART (USB)
`define NRV_IO_SSD1351 // Mapped IO, 128x128x64K OLED screen
`define NRV_IO_MAX7219 // Mapped IO, 8x8 led matrix
`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space. Can be used to run code from SPI flash.
/************************* Processor configuration *******************************************************************/
/*
`define NRV_FEMTORV32_TACHYON // "Tachyon" (carefully latched for max highfreq). Needs more space (remove MAX7219).
`define NRV_FREQ 60 // Validated at 60 MHz on the IceStick. Can overclock to 80-95 MHz.
`define NRV_RESET_ADDR 32'h00820000 // Jump execution to SPI Flash (800000h, +128k(20000h) for FPGA bitstream)
`define NRV_COUNTER_WIDTH 24 // Number of bits in cycles counter
`define NRV_TWOLEVEL_SHIFTER // Faster shifts
*/
// tinyraytracer: 90 MHz, 14:02
// 95 MHz, 13:18
`define NRV_FEMTORV32_QUARK
`define NRV_FREQ 50 // Validated at 50 MHz on the IceStick. Can overclock to 70 MHz.
`define NRV_RESET_ADDR 32'h00820000 // Jump execution to SPI Flash (800000h, +128k(20000h) for FPGA bitstream)
`define NRV_COUNTER_WIDTH 24 // Number of bits in cycles counter
`define NRV_TWOLEVEL_SHIFTER // Faster shifts
// tinyraytracer: 70 MHz, 17:30
/************************* RAM (in bytes, needs to be a multiple of 4)***********************************************/
`define NRV_RAM 6144 // default for ICESTICK (cannot do more !)
/************************* Advanced devices configuration ***********************************************************/
`define NRV_RUN_FROM_SPI_FLASH // Do not 'readmemh()' firmware from '.hex' file
`define NRV_IO_HARDWARE_CONFIG // Comment-out to disable hardware config registers mapped in IO-Space
// (note: firmware libfemtorv32 depends on it)
/********************************************************************************************************************/
`define NRV_CONFIGURED

35
RTL/CONFIGS/icesugarnano_config.v Normal file
View File

@@ -0,0 +1,35 @@
// Default femtosoc configuration file for iCESugar-nano (iCE40LP1KCM36)
/************************* Devices **********************************************************************************/
`define NRV_IO_LEDS // Mapped IO, LEDs D1,D2,D3,D4 (D5 is used to display errors)
//`define NRV_IO_IRDA // In IO_LEDS, support for the IRDA (WIP)
`define NRV_IO_UART // Mapped IO, virtual UART (USB)
//`define NRV_IO_SSD1351 // Mapped IO, 128x128x64K OLED screen
//`define NRV_IO_MAX7219 // Mapped IO, 8x8 led matrix
`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space. Can be used to run code from SPI flash.
/************************* Processor configuration *******************************************************************/
//`define NRV_FEMTORV32_TACHYON // "Tachyon" (carefully latched for max highfreq). Needs more space (remove MAX7219).
`define NRV_FEMTORV32_QUARK
`define NRV_FREQ 12 // 12 MHz is the default clock frequency in iCESugar-nano. Board max is 72 MHz.
`define NRV_RESET_ADDR 32'h00820000 // Jump execution to SPI Flash (800000h, +128k(20000h) for FPGA bitstream)
`define NRV_COUNTER_WIDTH 24 // Number of bits in cycles counter
//`define NRV_TWOLEVEL_SHIFTER // Faster shifts
//`define NRV_NEGATIVE_RESET
/************************* RAM (in bytes, needs to be a multiple of 4)***********************************************/
//`define NRV_RAM 4096 // 4kB, for less LUTs usage, edit spiflash_icesugar_nano.ld too for 4kB RAM
`define NRV_RAM 6144 // 6kB, default for iCESugar-nano (iCE40LP1KCM36) (cannot do more !)
/************************* Advanced devices configuration ***********************************************************/
`define NRV_RUN_FROM_SPI_FLASH // Do not 'readmemh()' firmware from '.hex' file
`define NRV_IO_HARDWARE_CONFIG // Comment-out to disable hardware config registers mapped in IO-Space
// (note: firmware libfemtorv32 depends on it)
/********************************************************************************************************************/
`define NRV_CONFIGURED

39
RTL/CONFIGS/ulx3s_config.v Normal file
View File

@@ -0,0 +1,39 @@
// Default femtosoc configuration file for ULX3S
/************************* Devices **********************************************************************************/
`define NRV_IO_LEDS // Mapped IO, LEDs D1,D2,D3,D4 (D5 is used to display errors)
`define NRV_IO_UART // Mapped IO, virtual UART (USB)
`define NRV_IO_SSD1331 // Mapped IO, 96x64x64K OLed screen
//`define NRV_IO_SSD1351 // Mapped IO, 128x128x64K OLed screen
//`define NRV_IO_MAX7219 // Mapped IO, 8x8 led matrix
`define NRV_IO_SDCARD // Mapped IO, SPI SDCARD
`define NRV_IO_BUTTONS // Mapped IO, buttons
`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space. Use with MINIRV32 to run code from SPI flash.
`define NRV_IO_FGA // Femto Graphic Adapter (ULX3S only)
/************************* Frequency ********************************************************************************/
`define NRV_FREQ 75 // Frequency in MHz. Recomm: 40 MHz Overclocking: 80 MHz
//`define NRV_FEMTORV32_QUARK // RV32I
//`define NRV_FEMTORV32_TACHYON // RV32I high freq
//`define NRV_FEMTORV32_QUARK_BICYCLE // RV32I 2 CPI
//`define NRV_FEMTORV32_ELECTRON // RV32IM
//`define NRV_FEMTORV32_GRACILIS // RV32IMC, IRQ
`define NRV_FEMTORV32_PETITBATEAU
`define NRV_RESET_ADDR 0 // The address the processor jumps to on reset
/************************* RAM (in bytes, needs to be a multiple of 4)***********************************************/
//`define NRV_RAM 393216 // bigger config for ULX3S
`define NRV_RAM 262144 // default for ULX3S
/************************* Advanced processor configuration *********************************************************/
`define NRV_IO_HARDWARE_CONFIG // Comment-out to disable hardware config registers mapped in IO-Space
// (only if you use your own firmware, libfemtorv32 depends on it)
/********************************************************************************************************************/
`define NRV_CONFIGURED