121 lines
3.8 KiB
Verilog
121 lines
3.8 KiB
Verilog
module RISCcore2 (
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input rst,
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input clk,
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output reg [31:0] pc,
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output reg [31:0] next_pc,
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output wire [31:0] instr
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);
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// IMem
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reg [31:0] imem [0:255];
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initial begin
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$readmemh("program.hex", imem);
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end
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assign instr = imem[pc[31:2]];
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// Decoder
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wire isUType = ((instr[6:0] == 7'b0110111) || (instr[6:0] == 7'b0010111));
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wire isIType = ((instr[6:0] == 7'b0000011) || (instr[6:0] == 7'b0000111) || (instr[6:0] == 7'b0010011) || (instr[6:0] == 7'b0011011) || (instr [6:0] == 7'b1100111));
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wire isRType = ((instr[6:0] == 7'b0101111) || (instr[6:0] == 7'b0110011) || (instr[6:0] == 7'b0111011));
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wire isSType = ((instr[6:0] == 7'b0100011) || (instr[6:0] == 7'b0100111));
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wire isBType = (instr[6:0] == 7'b1100011);
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wire isJType = (instr[6:0] == 7'b1101111);
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wire [4:0] rs1 = instr[19:15];
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wire [4:0] rs2 = instr[24:20];
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wire [4:0] rd = instr[11:7];
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wire rs2Valid = (isRType || isSType || isBType);
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wire rs1Valid = (~isUType && ~isJType);
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wire rdValid = (~isSType && ~isBType);
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wire [3:0] funct3 = instr[14:12];
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wire [6:0] funct7 = instr[31:25];
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// FIXED: Removed extra spaces in immediate concatenations
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wire [31:0] Iimm = {{21{instr[31]}}, instr[30:25], instr[24:20]};
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wire [31:0] Simm = {{21{instr[31]}}, instr[30:25], instr[11:7]};
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wire [31:0] Bimm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
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wire [31:0] Uimm = {instr[31], instr[30:20], instr[19:12], {12{1'b0}}};
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wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:25], instr[24:21], 1'b0};
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// Instructions
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wire isBEQ = (funct3 == 3'b000 && isBType);
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wire isBNE = (funct3 == 3'b001 && isBType);
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wire isBLT = (funct3 == 3'b100 && isBType);
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wire isBGE = (funct3 == 3'b101 && isBType);
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wire isBLTU = (funct3 == 3'b110 && isBType);
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wire isBGEU = (funct3 == 3'b111 && isBType);
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wire isADDI = (funct3 == 3'b000 && isIType);
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wire isADD = (funct7[5] == 1'b0 && isRType && (funct3 == 3'b000));
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// Register file signals
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wire rf_wr_en;
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wire [4:0] rf_wr_index;
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wire [31:0] rf_wr_data;
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wire rf_rd_en1, rf_rd_en2;
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wire [4:0] rf_rd_index1, rf_rd_index2;
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wire [31:0] rf_rd_data1, rf_rd_data2;
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wire [31:0] src1_value, src2_value;
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// Connect register file read ports
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assign rf_rd_en1 = rs1Valid;
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assign rf_rd_en2 = rs2Valid;
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assign rf_rd_index1 = rs1;
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assign rf_rd_index2 = rs2;
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// Connect outputs
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assign src1_value = rf_rd_data1;
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assign src2_value = rf_rd_data2;
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// ALU FOR ADD, ADDI
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wire [31:0] alu_result;
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wire [31:0] alu_op2 = isADDI ? Iimm : src2_value;
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assign alu_result = (isADDI || isADD) ? (src1_value + alu_op2) : 32'b0;
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// x0 support adding
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assign rf_wr_data = rf_wr_en ? alu_result : 32'b0;
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assign rf_wr_en = rdValid && (isADD || isADDI) && (rd != 5'b0);
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assign rf_wr_index = rd;
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// Branch logic
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wire taken_br;
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wire [31:0] br_tgt_pc;
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// Manual signed comparison for BLT and BGE
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wire signed_lt = (src1_value[31] && !src2_value[31]) ? 1'b1 : // src1 negative, src2 positive
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(!src1_value[31] && src2_value[31]) ? 1'b0 : // src1 positive, src2 negative
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(src1_value < src2_value); // same sign, compare normally
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wire signed_ge = (src1_value[31] && !src2_value[31]) ? 1'b0 : // src1 negative, src2 positive
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(!src1_value[31] && src2_value[31]) ? 1'b1 : // src1 positive, src2 negative
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(src1_value >= src2_value); // same sign, compare normally
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// Branch condition calculation
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assign taken_br =
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isBEQ ? (src1_value == src2_value) :
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isBNE ? (src1_value != src2_value) :
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isBLT ? signed_lt :
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isBGE ? signed_ge :
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isBLTU ? (src1_value < src2_value) :
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isBGEU ? (src1_value >= src2_value) :
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1'b0;
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// Branch target calculation
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assign br_tgt_pc = pc + Bimm;
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// PC logic
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always @(posedge clk) begin
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if(rst) begin
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pc <= 32'h0;
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next_pc <= 32'h4;
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end
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else begin
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next_pc <= taken_br ? br_tgt_pc : (pc + 32'h4);
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pc <= next_pc;
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end
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end
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endmodule
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