39 lines
692 B
Verilog
39 lines
692 B
Verilog
module RISCcore2TB;
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reg clk;
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reg rst;
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wire [31:0] pc;
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wire [31:0] next_pc;
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wire [31:0] instr;
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// Instantiate RISC core
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RISCcore2 uut (
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.rst(rst),
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.clk(clk),
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.pc(pc),
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.next_pc(next_pc),
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.instr(instr)
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);
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// Clock generation
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always #5 clk = ~clk;
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// Monitor
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always @(posedge clk) begin
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$display("Time=%0t, PC=%h, Instr=%h", $time, pc, instr);
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if (pc == 32'h100) begin // End simulation after some time
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$display("Simulation completed successfully!");
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$finish;
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end
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end
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// Initialize
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initial begin
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clk = 0;
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rst = 1;
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#10 rst = 0;
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#200;
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$display("Test completed");
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$finish;
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end
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endmodule
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