205 lines
7.5 KiB
Verilog
205 lines
7.5 KiB
Verilog
module RISCcore2 (
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input rst,
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input clk,
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output reg [31:0] pc,
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output wire [31:0] next_pc, // Changed to wire
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output wire [31:0] instr
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);
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// IMem - reduced size for simplicity
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reg [31:0] imem [0:63];
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initial begin
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$readmemh("program.hex", imem);
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end
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assign instr = imem[pc[31:2]]; // Word-aligned access
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// Instruction decoder
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wire [6:0] opcode = instr[6:0];
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wire [4:0] rs1 = instr[19:15];
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wire [4:0] rs2 = instr[24:20];
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wire [4:0] rd = instr[11:7];
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wire [2:0] funct3 = instr[14:12];
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wire [6:0] funct7 = instr[31:25];
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// Instruction type detection
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wire isUType = (opcode == 7'b0110111) || (opcode == 7'b0010111); // LUI, AUIPC
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wire isIType = (opcode == 7'b0000011) || (opcode == 7'b0000111) || // LOAD
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(opcode == 7'b0010011) || (opcode == 7'b0011011) || // OP-IMM
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(opcode == 7'b1100111); // JALR
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wire isRType = (opcode == 7'b0110011) || (opcode == 7'b0111011); // OP
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wire isSType = (opcode == 7'b0100011) || (opcode == 7'b0100111); // STORE
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wire isBType = (opcode == 7'b1100011); // BRANCH
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wire isJType = (opcode == 7'b1101111); // JAL
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// Immediate generation
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wire [31:0] Iimm = {{20{instr[31]}}, instr[31:20]};
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wire [31:0] Simm = {{20{instr[31]}}, instr[31:25], instr[11:7]};
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wire [31:0] Bimm = {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
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wire [31:0] Uimm = {instr[31:12], 12'b0};
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wire [31:0] Jimm = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
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// Register file
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reg [31:0] rf [0:31];
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// Initialize register file (x0 always zero)
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integer i;
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initial begin
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for (i = 0; i < 32; i = i + 1) begin
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rf[i] = 32'b0;
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end
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end
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// Read ports
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wire [31:0] rs1_val = (rs1 != 0) ? rf[rs1] : 32'b0;
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wire [31:0] rs2_val = (rs2 != 0) ? rf[rs2] : 32'b0;
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// Instruction decoding
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wire isADDI = (isIType) && (funct3 == 3'b000);
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wire isADD = (isRType) && (funct3 == 3'b000) && (funct7 == 7'b0000000);
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// Branch instructions
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wire isBEQ = (isBType) && (funct3 == 3'b000);
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wire isBNE = (isBType) && (funct3 == 3'b001);
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wire isBLT = (isBType) && (funct3 == 3'b100);
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wire isBGE = (isBType) && (funct3 == 3'b101);
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wire isBLTU = (isBType) && (funct3 == 3'b110);
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wire isBGEU = (isBType) && (funct3 == 3'b111);
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//store load instructions
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wire isLB = (isIType) && (funct3 == 3'b000);
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wire isLH = (isIType) && (funct3 == 3'b001);
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wire isLW = (isIType) && (funct3 == 3'b010);
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wire isLBU = (isIType) && (funct3 == 3'b100);
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wire isLHU = (isIType) && (funct3 == 3'b101);
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wire isSB = (isSType) && (funct3 == 3'b000);
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wire isSH = (isSType) && (funct3 == 3'b001);
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wire isSW = (isSType) && (funct3 == 3'b010);
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//sl and sr instructions
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wire isSLT = (isRType) && (funct3 == 3'b010) && (funct7[5] == 1'b0);
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wire isSLTU = (isRType) && (funct3 == 3'b011) && (funct7[5] == 1'b0);
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wire isSLL = (isRType) && (funct3 == 3'b001) && (funct7[5] == 1'b0);
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wire isSLTI = (isIType) && (funct3 == 3'b010);
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wire isSLTIU = (isIType) && (funct3 == 3'b011);
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wire isSRA = (isRType) && (funct3 == 3'b101) && (funct7[5] == 1'b1);
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wire isSRL = (isRType) && (funct3 == 3'b101) && (funct7[5] == 1'b0);
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wire isSRAI = (isIType) && (funct3 == 3'b101) && (funct7[5] == 1'b1);
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wire isSLLI = (isIType) && (funct3 == 3'b001) && (funct7[5] == 1'b0);
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wire isSRLI = (isIType) && (funct3 == 3'b101) && (funct7[5] == 1'b0);
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//logic imms
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wire isANDI = (isIType) && (funct3 == 3'b111);
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wire isORI = (isIType) && (funct3 == 3'b110);
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wire isXORI = (isIType) && (funct3 == 3'b100);
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// logic
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wire isAND = (isRType) && (funct3 == 3'b111) && (funct7[5] == 1'b0);
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wire isOR = (isRType) && (funct3 == 3'b110) && (funct7[5] == 1'b0);
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wire isXOR = (isRType) && (funct3 == 3'b100) && (funct7[5] == 1'b0);
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wire isSUB = (isRType) && (funct3 == 3'b000) && (funct7[5] == 1'b1);
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//lui auipc (opcode use)
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wire isLUI = (opcode == 7'b0110111);
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wire isAUIPC = (opcode == 7'b0010111);
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wire isJAL = (opcode == 7'b1101111);
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//jal UType
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wire isJALR = (opcode == 7'b1100111) && (funct3 == 3'b000);
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// ALU operations
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//sltu and slt
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wire [31:0] sltu_rslt = {31'b0, (rs1_val < rs2_val)};
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wire [31:0] signed_slt = (rs1_val[31] && !rs2_val[31]) ? 1'b1 :
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(!rs1_val[31] && rs2_val[31]) ? 1'b0 :
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(rs1_val < rs2_val);
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wire [31:0] slt_rslt = {31'b0, signed_slt};
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wire [31:0] slti_rslt = ((rs1_val[31] == Iimm[31]) ? sltu_rslt : {31'b0, rs1_val[31]});
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wire [63:0] SErs1_val = {32{rs1_val[31]}, (rs1_val < rs2_val)};
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wire [63:0] sra_rslt = {SErs1_val >> rs2_val[4:0]};
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wire [63:0] srai_rslt = {SErs1_val >> Iimm[4:0]};
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wire [31:0] sltiu_rslt = {31'b0, (rs1_val < Iimm)};
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wire [31:0] alu_result = (isADDI) ? (rs1_val + Iimm) :
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(isADD) ? (rs1_val + rs2_val) :
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(isSLT) ? slt_rslt :
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(isSLTU) ? sltu_rslt :
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(isSRA) ? sra_rslt :
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(isSRAI) ? srai_rslt :
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(isSLTI) ? slti_rslt :
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(isANDI) ? (rs1_val & Iimm) :
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(isORI) ? (rs1_val | Iimm) :
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(isXORI) ? (rs1_val ^ Iimm) :
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(isSLLI) ? (rs1_val << Iimm[5:0]) :
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(isSRLI) ? (rs1_val >> Iimm[5:0]) :
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(isAND) ? (rs1_val & rs2_val) :
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(isOR) ? (rs1_val | rs2_val) :
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(isXOR) ? (rs1_val ^ rs2_val) :
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(isSUB) ? (rs1_val - rs2_val) :
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(isSLL) ? (rs1_val << rs2_val[4:0]) :
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(isSRL) ? (rs1_val >> rs2_val[4:0]) :
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(isSLTIU) ? (sltiu_rslt) :
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(isLUI) ? ({Iimm[31:12], 12'b0}) :
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(isAUIPC) ? (pc + Iimm) :
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(isJAL) ? (pc + 32'd4) :
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(isJALR) ? (pc + 32'd4) :
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(isSRA) ? (sra_rslt[31:0]) :
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(isSRAI) ? (srai_rslt[31:0]) :
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32'b0;
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// Branch condition logic
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wire signed [31:0] signed_rs1 = rs1_val;
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wire signed [31:0] signed_rs2 = rs2_val;
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wire branch_taken =
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isBEQ ? (rs1_val == rs2_val) :
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isBNE ? (rs1_val != rs2_val) :
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isBLT ? (signed_rs1 < signed_rs2) :
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isBGE ? (signed_rs1 >= signed_rs2) :
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isBLTU ? (rs1_val < rs2_val) :
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isBGEU ? (rs1_val >= rs2_val) :
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1'b0;
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// Next PC calculation - FIXED: using wire for continuous assignment
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wire [31:0] branch_target = pc + Bimm;
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wire [31:0] next_pc_base = pc + 32'h4;
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assign next_pc = branch_taken ? branch_target : next_pc_base;
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// Register write back
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wire rf_write_enable = (rd != 0) && (isADDI || isADD);
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wire [31:0] writeback_data = alu_result;
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// PC update
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always @(posedge clk) begin
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if (rst) begin
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pc <= 32'h0;
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end else begin
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pc <= next_pc;
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end
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end
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// Register write back
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always @(posedge clk) begin
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if (rf_write_enable && !rst) begin
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rf[rd] <= writeback_data;
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$display("RF Write: x%d = %h", rd, writeback_data);
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end
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end
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// Debug monitoring
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always @(posedge clk) begin
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if (!rst) begin
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$display("PC=%08h, Instr=%08h, rs1=x%d(%h), rs2=x%d(%h), rd=x%d, branch_taken=%b",
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pc, instr, rs1, rs1_val, rs2, rs2_val, rd, branch_taken);
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if (pc[1:0] != 2'b00) begin
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$display("WARNING: PC not word-aligned: %h", pc);
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end
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end
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end
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endmodule
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