56 lines
1.1 KiB
Verilog
56 lines
1.1 KiB
Verilog
module RISCCore_tb;
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reg clk;
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reg rst;
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wire [31:0] pc;
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wire [31:0] next_pc;
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wire [31:0] instr;
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// Instantiate the RISC-V core
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RISCCore uut (
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.rst(rst),
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.clk(clk),
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.pc(pc),
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.next_pc(next_pc),
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.instr(instr)
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);
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// Clock generation
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always #5 clk = ~clk;
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// Test sequence
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initial begin
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// Initialize signals
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clk = 0;
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rst = 1;
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// Apply reset
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#10 rst = 0;
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// Run for 100 clock cycles
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#1000;
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// Display final register values
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$display("\n=== Final Register Values ===");
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for (integer i = 0; i < 32; i = i + 1) begin
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if (uut.rf[i] != 0) begin
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$display("x%d = %h", i, uut.rf[i]);
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end
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end
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// Display final memory contents
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$display("\n=== Final Memory Contents ===");
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for (integer i = 0; i < 32; i = i + 1) begin
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if (uut.dmem[i] != 0) begin
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$display("Mem[%d] = %h", i, uut.dmem[i]);
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end
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end
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$finish;
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end
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// Monitor important signals
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initial begin
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$monitor("Time=%0t, PC=%h, Instr=%h", $time, pc, instr);
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end
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endmodule
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