29 lines
298 B
Verilog
29 lines
298 B
Verilog
module pcTB();
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reg clk;
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reg rst;
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wire [31:0] pc;
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wire [31:0] next_pc;
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pc uut (
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.clk(clk),
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.rst(rst),
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.pc(pc),
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.next_pc(next_pc)
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);
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always begin
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clk = ~clk; #2;
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end
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initial begin
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$dumpfile("pc.vcd");
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$dumpvars;
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clk = 0;
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rst = 1; #4;
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rst = 0; #80;
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$finish;
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end
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endmodule
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