46 lines
654 B
Verilog
46 lines
654 B
Verilog
module calculator (
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input [1:0] op,
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input clk,
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input rst,
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output reg [31:0] Y
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);
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reg [31:0] A;
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reg [31:0] B;
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wire [5:0] B_rand;
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wire [3:0] A_rand;
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reg [31:0] Y_prev;
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assign A = {{28{1'b0}}, A_rand[5:0]};
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assign B = {{26{1'b0}}, B_rand[3:0]};
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always @(*) begin
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if(!rst) begin
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case(op)
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2'b00 :Y = A + B;
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2'b01 :Y = A - B;
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2'b10 :Y = A * B;
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2'b11 :Y = A / B;
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default: Y = 0;
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endcase
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end
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else begin
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Y = 0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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Y_prev <= 32'd0;
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A <= 32'd0;
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B <= 32'd0;
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end
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else begin
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Y_prev <= Y;
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A <= Y_prev;
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end
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end
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endmodule
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