24 lines
280 B
Verilog
24 lines
280 B
Verilog
module fibonacciTB();
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reg clk, rst;
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wire [31:0] num;
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fibonacci uut (
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.clk(clk),
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.rst(rst),
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.num(num)
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);
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always begin
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clk = ~clk; #1;
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end
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initial begin
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$dumpfile("fibonacci.vcd");
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$dumpvars;
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clk = 1'b0; rst = 1'b1; #4;
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rst = 1'b0; #40;
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$finish;
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end
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endmodule
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