35 lines
408 B
Verilog
35 lines
408 B
Verilog
module pcIMem (
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input rst,
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input clk,
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output reg [31:0] pc,
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output reg [31:0] next_pc,
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output wire [31:0] instr
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);
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//PC
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always @(posedge clk) begin
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if(rst) begin
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pc <= 32'h0;
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end
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else begin
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next_pc <= pc;
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pc <= pc + 32'h4;
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end
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end
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//IMem
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reg [31:0] imem [0:255];
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initial begin
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$readmemh("program.hex", imem);
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end
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assign instr = imem[pc[31:2]];
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//Decoder
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r
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endmodule
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