module pcTB();

reg clk;
reg rst;
wire [31:0] pc;
wire [31:0] next_pc;

pc uut (
  .clk(clk),
  .rst(rst),
  .pc(pc),
  .next_pc(next_pc)
);

always begin 
  clk = ~clk; #2;
end

initial begin 
  $dumpfile("pc.vcd");
  $dumpvars;
  clk = 0;
  rst = 1; #4;
  rst = 0; #80;
  $finish;
end

endmodule