module calculator (
  input [1:0] op,
  input clk,
  input rst,
  output reg [31:0] Y
);

reg [31:0] A;
reg [31:0] B;

wire [5:0] B_rand;
wire [3:0] A_rand;

reg [31:0] Y_prev;

assign A = {{28{1'b0}}, A_rand[5:0]};
assign B = {{26{1'b0}}, B_rand[3:0]};

always @(*) begin
  if(!rst) begin
    case(op)
      2'b00 :Y =  A + B;
      2'b01 :Y =  A - B;
      2'b10 :Y =  A * B;
      2'b11 :Y =  A / B;
      default: Y = 0;
    endcase
  end 
  else begin 
    Y = 0;
  end
end

always @(posedge clk) begin
  if (rst) begin 
    Y_prev <= 32'd0;
    A <= 32'd0;
    B <= 32'd0;
  end 
  else begin 
    Y_prev <= Y;
    A <= Y_prev;
  end
end
endmodule