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todo:ALUfix

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kaltinsoy
2025-08-21 21:03:41 +03:00
parent 3c2407543d
commit e39daed967
2 changed files with 442 additions and 416 deletions
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44
chapter5/RISCcore2.v
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@@ -54,16 +54,37 @@ module RISCcore2 (
wire [31:0] rs2_val = (rs2 != 0) ? rf[rs2] : 32'b0;
// Instruction decoding
wire isADDI = (opcode == 7'b0010011) && (funct3 == 3'b000);
wire isADD = (opcode == 7'b0110011) && (funct3 == 3'b000) && (funct7 == 7'b0000000);
wire isADDI = (isIType) && (funct3 == 3'b000);
wire isADD = (isRType) && (funct3 == 3'b000) && (funct7 == 7'b0000000);
// Branch instructions
wire isBEQ = (opcode == 7'b1100011) && (funct3 == 3'b000);
wire isBNE = (opcode == 7'b1100011) && (funct3 == 3'b001);
wire isBLT = (opcode == 7'b1100011) && (funct3 == 3'b100);
wire isBGE = (opcode == 7'b1100011) && (funct3 == 3'b101);
wire isBLTU = (opcode == 7'b1100011) && (funct3 == 3'b110);
wire isBGEU = (opcode == 7'b1100011) && (funct3 == 3'b111);
wire isBEQ = (isBType) && (funct3 == 3'b000);
wire isBNE = (isBType) && (funct3 == 3'b001);
wire isBLT = (isBType) && (funct3 == 3'b100);
wire isBGE = (isBType) && (funct3 == 3'b101);
wire isBLTU = (isBType) && (funct3 == 3'b110);
wire isBGEU = (isBType) && (funct3 == 3'b111);
//store load instructions
wire isLB = (isIType) && (funct3 == 3'b000);
wire isLH = (isIType) && (funct3 == 3'b001);
wire isLW = (isIType) && (funct3 == 3'b010);
wire isLBU = (isIType) && (funct3 == 3'b100);
wire isLHU = (isIType) && (funct3 == 3'b101);
wire isSB = (isSType) && (funct3 == 3'b000);
wire isSH = (isSType) && (funct3 == 3'b001);
wire isSW = (isSType) && (funct3 == 3'b010);
//sl and sr instructions
wire isSLT = (isRType) && (funct3 == 3'b010) && (funct7[5] == 1'b0);
wire isSLTU = (isRType) && (funct3 == 3'b011) && (funct7[5] == 1'b0);
wire isSLL = (isRType) && (funct3 == 3'b001) && (funct7[5] == 1'b0);
wire isSLTI = (isIType) && (funct3 == 3'b010);
wire isSLTIU = (isIType) && (funct3 == 3'b011);
wire isSRA = (isRType) && (funct3 == 3'b101) && (funct7[5] == 1'b1);
wire isSRL = (isRType) && (funct3 == 3'b101) && (funct7[5] == 1'b0);
// ALU operations
wire [31:0] alu_src2 = isADDI ? Iimm : rs2_val;
@@ -72,7 +93,12 @@ module RISCcore2 (
// Branch condition logic
wire signed [31:0] signed_rs1 = rs1_val;
wire signed [31:0] signed_rs2 = rs2_val;
//sltu and slt
wire [31:0] sltu_rslt = {31'b0, (src)}
wire branch_taken =
isBEQ ? (rs1_val == rs2_val) :
isBNE ? (rs1_val != rs2_val) :