From a40879f631420708670f73484c529261919ef9b1 Mon Sep 17 00:00:00 2001 From: kaltinsoy Date: Fri, 22 Aug 2025 07:14:22 +0300 Subject: [PATCH] aluAdded --- chapter5/RISCcore2.v | 70 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 63 insertions(+), 7 deletions(-) diff --git a/chapter5/RISCcore2.v b/chapter5/RISCcore2.v index b74cd0f..f0dca8c 100644 --- a/chapter5/RISCcore2.v +++ b/chapter5/RISCcore2.v @@ -85,19 +85,75 @@ module RISCcore2 ( wire isSRA = (isRType) && (funct3 == 3'b101) && (funct7[5] == 1'b1); wire isSRL = (isRType) && (funct3 == 3'b101) && (funct7[5] == 1'b0); + wire isSRAI = (isIType) && (funct3 == 3'b101) && (funct7[5] == 1'b1); + + wire isSLLI = (isIType) && (funct3 == 3'b001) && (funct7[5] == 1'b0); + wire isSRLI = (isIType) && (funct3 == 3'b101) && (funct7[5] == 1'b0); + + //logic imms + wire isANDI = (isIType) && (funct3 == 3'b111); + wire isORI = (isIType) && (funct3 == 3'b110); + wire isXORI = (isIType) && (funct3 == 3'b100); + + // logic + wire isAND = (isRType) && (funct3 == 3'b111) && (funct7[5] == 1'b0); + wire isOR = (isRType) && (funct3 == 3'b110) && (funct7[5] == 1'b0); + wire isXOR = (isRType) && (funct3 == 3'b100) && (funct7[5] == 1'b0); + wire isSUB = (isRType) && (funct3 == 3'b000) && (funct7[5] == 1'b1); + + //lui auipc (opcode use) + wire isLUI = (opcode == 7'b0110111); + wire isAUIPC = (opcode == 7'b0010111); + wire isJAL = (opcode == 7'b1101111); + //jal UType + + wire isJALR = (opcode == 7'b1100111) && (funct3 == 3'b000); // ALU operations - wire [31:0] alu_src2 = isADDI ? Iimm : rs2_val; - wire [31:0] alu_result = (isADDI || isADD) ? (rs1_val + alu_src2) : 32'b0; + //sltu and slt + wire [31:0] sltu_rslt = {31'b0, (rs1_val < rs2_val)}; + wire [31:0] signed_slt = (rs1_val[31] && !rs2_val[31]) ? 1'b1 : + (!rs1_val[31] && rs2_val[31]) ? 1'b0 : + (rs1_val < rs2_val); + wire [31:0] slt_rslt = {31'b0, signed_slt}; + wire [31:0] slti_rslt = ((rs1_val[31] == Iimm[31]) ? sltu_rslt : {31'b0, rs1_val[31]}); + + wire [63:0] SErs1_val = {32{rs1_val[31]}, (rs1_val < rs2_val)}; + + wire [63:0] sra_rslt = {SErs1_val >> rs2_val[4:0]}; + wire [63:0] srai_rslt = {SErs1_val >> Iimm[4:0]}; + wire [31:0] sltiu_rslt = {31'b0, (rs1_val < Iimm)}; + + wire [31:0] alu_result = (isADDI) ? (rs1_val + Iimm) : + (isADD) ? (rs1_val + rs2_val) : + (isSLT) ? slt_rslt : + (isSLTU) ? sltu_rslt : + (isSRA) ? sra_rslt : + (isSRAI) ? srai_rslt : + (isSLTI) ? slti_rslt : + (isANDI) ? (rs1_val & Iimm) : + (isORI) ? (rs1_val | Iimm) : + (isXORI) ? (rs1_val ^ Iimm) : + (isSLLI) ? (rs1_val << Iimm[5:0]) : + (isSRLI) ? (rs1_val >> Iimm[5:0]) : + (isAND) ? (rs1_val & rs2_val) : + (isOR) ? (rs1_val | rs2_val) : + (isXOR) ? (rs1_val ^ rs2_val) : + (isSUB) ? (rs1_val - rs2_val) : + (isSLL) ? (rs1_val << rs2_val[4:0]) : + (isSRL) ? (rs1_val >> rs2_val[4:0]) : + (isSLTIU) ? (sltiu_rslt) : + (isLUI) ? ({Iimm[31:12], 12'b0}) : + (isAUIPC) ? (pc + Iimm) : + (isJAL) ? (pc + 32'd4) : + (isJALR) ? (pc + 32'd4) : + (isSRA) ? (sra_rslt[31:0]) : + (isSRAI) ? (srai_rslt[31:0]) : + 32'b0; // Branch condition logic wire signed [31:0] signed_rs1 = rs1_val; wire signed [31:0] signed_rs2 = rs2_val; - - //sltu and slt - wire [31:0] sltu_rslt = {31'b0, (src)} - - wire branch_taken = isBEQ ? (rs1_val == rs2_val) :