riscv single cycle

chapter4/pcIMemDec.v

@@ -58,15 +58,51 @@ wire [31:0] Jimm = {{12{instr[31]}}, {instr[19:12]}, {instr[20]}, {instr[30:25]}
 
 //Instructions
 
-isBEQ = (funct3 == 000 && isBType);
-isBNE = (funct3 == 001 && isBType);
-isBLT = (funct3 == 100 && isBType);
-isBGE = (funct3 == 101 && isBType);
-isBLTU = (funct3 == 110 && isBType);
-isBGEU = (funct3 == 111 && isBType);
+isBEQ = (funct3 == 3'b000 && isBType);
+isBNE = (funct3 == 3'b001 && isBType);
+isBLT = (funct3 == 3'b100 && isBType);
+isBGE = (funct3 == 3'b101 && isBType);
+isBLTU = (funct3 == 3'b110 && isBType);
+isBGEU = (funct3 == 3'b111 && isBType);
 
-isADDI = (funct3 == 000 && isIType);
+isADDI = (funct3 == 3'b000 && isIType);
 
-isADD = (funct7[5] == 0 && isRType);
+isADD = (funct7[5] == 1'b0 && isRType);
+
+isLW = (funct3 == 3'b010 && isIType);
+isSW = (funct3 == 3'b010 && isSType);
+
+//Register file
+
+wire rf_wr_en;
+wire [4:0] rf_wr_index;
+wire [31:0] rf_wr_data;
+wire rf_rd_en1, rf_rd_en2;
+wire [4:0] rf_rd_index1, rf_rd_index2;
+
+wire rf_rd_data1, rf_rd_data2;
+
+wire src1_value, src2_value;
+
+assign rf_rd_en1 = rs1Valid;
+assign rf_rd_en2 = rs2Valid;
+
+assign rf_rd_index1 = rs1;
+assign rf_rd_index2 = rs2;
+
+assign src1_value = rf_rd_data1;
+assign src2_value = rf_rd_data2;
+
+/* Maybe write logic ?
+assign rf_wr_en = 1'b0;
+assign rf_wr_index = 5'b0;
+assign rf_wr_data = 32'b0;
+Disabled */
+
+// ALU FOR ADD, ADDI 
+wire [31:0] alu_result = 32'b0;
+wire [31:0] alu_op2 = isADDI ? Iimm : src2_value;
+
+assign alu_result = (isADDI || isADD) ? (src1_value + alu_op2) : 32'b0;
 
 endmodule